A STUDY OF ULTRASMALL DEVICE CONTAINING NANOMETER-CONTROLLED Si-Ge HETEROLAYER

含纳米控制Si-Ge异质层的超小型器件的研究

基本信息

批准号：
04452167
负责人：
MUROTA Junichi
金额：
$ 3.71万
依托单位：
TOHOKU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1992
资助国家：
日本
起止时间：
1992 至 1993
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-04452167/
关键词：
Silicon Silicon-Germanium Heterostructure Heterodevice Ultrasmall Device CVD MOSFET

项目摘要

The object of this research is to construct the fabrication process of a high performance ultrasmall device containing nanometer controlled Si_<1-x>Ge_x heterolayr. The research results are summarized as follows.(1) A very low-temperature epitaxial growth process of the Si/Si_<1-x>Ge_x/Si heterostructure with atomically flat surfaces and interfaces for Ge fractions on Si(100) has been achieved under the cleanest possible reaction and interfaces for Ge fracions on Si(100) has been achieved under the cleanest possible reaction environment of SiH_4, GeH_4 and H_2 or Ar using an ultraclean hot-wall low-pressure CVD system. A relatively lower deposition temperatures were suitable for higher Ge fractions in order to prevent island growth of thelayrs during deposition. Atomically flat surfaces and interfaces for the heterostructure containing Si_<0.8>Ge_<0.2>, Si_<0.5>Ge_<0.5> and Si_<0.3>Ge_<0.7> layrs were obtained by deposition at 550, 500 and 450ﾟC, respectively.(2) MOSFET's were fabricated at temparetures below 700ﾟC on the 10nm-thick Si/7nm-thick Si_<1-x>Ge_x/Si heterostructure using a self-alligned Si gate process. A high performance Si_<0.5>Ge_<0.5>-channel MOSFET has been achieved with a large mobility enhancement of about 70% at 300K and over 150% at 77K compared with that of a MOSFET without SiGe-channel.(3) In-situ B doping control of Si_<1-x>Ge_x layr was achieved in the range of 3x10^<17>-2x10^<20>cm^<-3>. It was found that Hall mobility has a minimum value for Si_<0.75>Ge_<0.25> film, and the mobility of the strained Si_<0.75>Ge_<0.25> film is neary equal to that of the unstrained one.(4) In-sity B doped selective SiGe epitaxial growth were achieved at 550ﾟC.Using this selective film, high performance self-aligned ultrashallow junction was formed with a low level reverse current density, the range of 10^<-10>A/cm^2. As a result, the overlap control between gate and source/drain and suppression of short channel effects in ultrasmall MOSFET can be improved.

这项研究的目的是构建具有纳米控制的Si_ <1-X> GE_X Heterolayr的高性能超大设备的制造过程。总结如下。（1）Si/Si_ <1-x> ge_x/si异质结构的si/si_ <1-x> ge_x/si异质结构非常低的外在外观增长过程，在SI（100）上，在Si（100）上，在SI的si（100）中，在SI（100）上，SI-ext ext the Exect的si（100）实现了SI（100）的互动（100）的si（100），这是SI的互动（100）的影响（100）。 GEH_4和H_2或使用UltraClean热壁低压CVD系统的AR。相对较低的沉积温度适用于较高的GE分数，以防止沉积过程中的岛屿生长。包含SI_ <0.8> ge_ <0.2>的异质结构的原子平坦表面和接口，Si_ <0.5> ge__ <0.5>和Si_ <0.3> ge__ <0.7> layrs通过沉积在550、500、500和450 c上的沉积中获得。 Si/7nm-Thick Si_ <1-X> GE_X/SI异构结构使用自称的Si Gate过程。高性能SI_ <0.5> GE_ <0.5> - 频道MOSFET已获得了300k时的大约70％的大约70％，而在77K时，与没有Sige-inge通道的MOSFET相比。（3）si_ <1-x> ge_x layr的Sige-b掺杂控制范围3x10^<17> -2x10^<20> cm^<-3>。发现Hall的移动性对于Si_ <0.75> GE_ <0.25>膜具有最低值，并且应变的Si_ <0.75> GE__ <0.25>膜的活动能力几乎等于未经培训的胶片。（4）（4）内置的选择性sige sige sige sige sige sige hige在550 c. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. c的。使用这种选择性膜，形成了高性能自我对齐的超柔糖连接，其水平反向电流密度低，范围为10^<-10> a/cm^2。结果，可以改善栅极和源/漏极之间的重叠控制，以及在Ultrasmall MOSFET中对短通道效应的抑制。