GOALI: Double-Gate Silicon on Insulator (SOI) Devise Consideration for Nano-Scale Design

GOALI：双栅极绝缘体上硅 (SOI) 设计考虑纳米级设计

• 批准号: 0221126
• 负责人: Dimitrios Ioannou
• 金额: $ 22.5万
• 依托单位: George Mason University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-09-15 至 2006-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0221126&HistoricalAwards=false
• 关键词: GOALI; Double; Gate; Silicon; Insulator

0221126IoannouThis is a proposal to carry out research on the interaction between device physics and circuit design using nano-scale double-gate SQI CMOS technology. Fully depleted, double-gate (FD-DG) S0I is currently recognized as the most suitable SOI version for nano-scale integration. Published research has focused on the physics of the device in isolation, in an effort to establish and examine the many attractive advantages, and connect them with the device design. However, viewed from the circuit point of view, more often than not these advantages come at the expense of higher capacitances and leakage currents, which (if unchecked) might degrade the circuit performance and reliability. It will be the central theme of the proposed research to seek out the subtleties of the devise design most relevant to circuit implementations, with the ultimate goal to skew the device design space towards better circuit performance, and suggest suitable circuit alternatives that derive maximum benefit from the use of DG devices. For example, it is not known a priori that the enhanced drive current of the DG transistor will make up for its enhanced capacitance, and one needs to examine the circuit topology for each of the DG structures available. Since DG structures suffer less from short channel effects (SCE) and supply double the current, thicker oxides can be used, which also lower the gate capacitance. Floating body effects (FBE) are thought to be inactive in DG structures; FBEs might, however, be triggered by deliberate (or otherwise) bias conditions, for example by inducing an overpopulation of holes in the body of an nMOS device. DG devices are currently been vigorously researched and evolving, and are commonly categorized as symmetric (SDG) and asymmetric (ADG). The SDG is a "normally on" device and for this and other reasons the favor is currently with the ADG device. Rather than modify the SDG device at the expense of complicated processing, the possibility will be investigated of using this intrinsically on structure as a load device for DG-SOI based ratioed logic, with ADG drivers.

0221126ioanthouthis是使用纳米级双门SQI CMOS技术进行对设备物理与电路设计之间相互作用进行研究的建议。目前，完全耗尽的双门（FD-DG）S0i被认为是用于纳米级集成的最合适的SOI版本。已发表的研究集中在孤立的设备物理上，以建立和检查许多有吸引力的优势，并将其与设备设计联系起来。但是，从电路的角度来看，这些优势通常以更高的电容和泄漏电流为代价，而电流（如果未经检查）可能会降低电路性能和可靠性。拟议研究的核心主题是寻找与电路实施最相关的设计的微妙之处，其最终目标是将设备设计空间偏向于更好的电路性能，并提出合适的电路替代方案，以最大程度地从使用DG设备中获得最大收益。例如，尚不清楚DG晶体管的增强驱动电流将弥补其增强的电容，并且需要检查每个可用DG结构的电路拓扑。由于DG结构受到短通道效应（SCE）的影响较小，并且供应两倍，因此可以使用较厚的氧化物，从而降低了栅极电容。浮动体效应（FBE）被认为在DG结构中是不活跃的。但是，FBE可能会由故意（或其他）偏置条件触发，例如，通过诱导NMOS设备体内孔的过度人口。目前，DG设备进行了大力研究和发展，通常被归类为对称（SDG）和不对称（ADG）。可持续发展目标是“通常在”设备上的“正常情况”，因此和其他原因是当前使用ADG设备。与其以复杂的处理为代价修改SDG设备，不如研究将其本质上的结构用作基于DG-SOI的基于DG-SOI的逻辑的负载设备，并与ADG驱动器一起使用。