Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC Designs

合作研究：SGER：基于双栅极晶体管阵列的 IC 设计的布局生成工具

• 批准号: 0904124
• 负责人: Malgorzata Marek-Sadowska
• 金额: $ 16.73万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-07-01 至 2011-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0904124&HistoricalAwards=false
• 关键词: Collaborative; Research; SGER; Layout; Generation

Title: Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC DesignsCCF - 0904122 Maly, Wojciech (Carnegie-Mellon University)CCF - 0904124 Marek-Sadowska, Malgorzata (University of California-Santa Barbara)ABSTRACTThe proposed project aims to demonstrate the feasibility of an approach that can potentially remedy the huge productivity crisis plaguing the IC industry. The PIs propose a design methodology utilizing transistor-array-based canvases. The building block of a canvas is a vertical slit (VeS), dual-gate, junction-less transistor that can be fabricated with an SOI-like process. Canvases can be configured into useful circuits by customizing interconnects fabricated in a metallization process. In this way, one of the show stoppers of the modern design, lithographic imperfections, can be almost completely eliminated. The research proposed here is focused on developing basic layout tools for VeS-transistor arrays to show that dense transistor layouts are feasible, and to quantify the performance and power consumption of circuits built from VeS transistors.If successful, the methodology may have a huge effect on IC manufacturing and design practices.The design and manufacturing strategy proposed here has a very real chance of helping designersto make rapid use of the huge number of transistors available on a single chip without sacrificing performance and cost. The VeS transistor arrays can also serve as foundations for 3-D integration.

标题：协作研究：SGER：基于双门透射阵列的布局生成工具基于IC Designsccf-0904122 Maly，Wojciech（Carnegie-Mellon University）CCF-0904124 MAREK-SADOWSKA，MAREK-SADOWSKA，MALGORZATKA，MALGORZATA（MALGORZATA）效力，拟议的是拟议的项目，该计划启示了拟议的项目，以示意拟议的项目，以示出拟议的项目。巨大的生产力危机困扰着IC行业。 PI提出了使用基于晶体管阵列的画布的设计方法。画布的构件是垂直缝隙（VES），双门，无连接的晶体管，可以用SOI般的过程进行制造。可以通过自定义金属化过程中制造的互连来将画布配置为有用的电路。这样，现代设计的表演阻止者之一即几乎可以完全消除。这里提出的研究重点是开发为VES-transtistor阵列开发基本的布局工具，以表明密集的晶体管布局是可行的，并量化了由VES晶体管构建的电路的性能和功耗。如果成功，该方法可能会对IC制造和制造量很大的单身效果具有很大的影响。牺牲绩效和成本。 VES晶体管阵列也可以用作3-D集成的基础。