Taylor Expansion Diagrams: A Compact Canonical Representation for RTL Verification

泰勒展开图：RTL 验证的紧凑规范表示

• 批准号: 0204146
• 负责人: Maciej Ciesielski
• 金额: $ 28万
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-07-01 至 2006-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0204146&HistoricalAwards=false
• 关键词: Taylor; Expansion; Diagrams; Compact; Canonical

The goal of this work is to develop a new canonical representation and an efficient verification infrastructure to support the RTL verification of large designs. The proposed graph-based representation, called Taylor Expansion Diagram, is based on a different decomposition principle than used by decisiondiagrams such as BDDs and BMDs. It is obtained by treating the symbolic expression of the design as a continuous, differentiable function and applying Taylor series expansion with respect to its word-level variables. The resulting Taylor Expansion Diagram (TED) is canonical for a fixed ordering of variables. TEDs can be used to represent functions containing both algebraic and Boolean expressions, facilitating the representation of complex designs with arithmetic operators and Boolean logic, typically encountered in RTL specifications. We are building an RTL verification infrastructure centered around TED that can be used to verify functional equivalence of RTL designs. We are developing systematic, algorithmic techniques for constructing and manipulating TED representations of HDL designs, based on the new theory.We are also investigating how to exploit TEDs for implementation verification, that is checking functional equivalence between an RTL specification and its logic, gate-level implementation. By carrying out extensive experiments, the applicability of TEDs to realistic designs with arithmetic circuits and Boolean logic must be evaluated, and the performance of TEDs compared against that of BDDs and *BMDs.This project has also an important educational role of teaching students about modern design representations from decision diagrams to more abstract, word-level data structures in the context of design synthesis and verification.

这项工作的目标是开发一种新的规范表示和高效的验证基础设施，以支持大型设计的 RTL 验证。所提出的基于图形的表示称为泰勒展开图，它基于与 BDD 和 BMD 等决策图所使用的分解原理不同的分解原理。它是通过将设计的符号表达视为连续的、可微的函数并对其字级变量应用泰勒级数展开来获得的。生成的泰勒展开图 (TED) 对于变量的固定顺序来说是规范的。 TED 可用于表示包含代数和布尔表达式的函数，从而有助于使用算术运算符和布尔逻辑来表示复杂设计，这通常在 RTL 规范中遇到。我们正在构建一个以 TED 为中心的 RTL 验证基础设施，可用于验证 RTL 设计的功能等效性。 我们正在开发基于新理论的系统算法技术，用于构建和操作 HDL 设计的 TED 表示。我们还在研究如何利用 TED 进行实现验证，即检查 RTL 规范与其逻辑、门控之间的功能等效性。级实施。 通过进行广泛的实验，必须评估 TED 对算术电路和布尔逻辑的实际设计的适用性，并将 TED 的性能与 BDD 和 *BMD 进行比较。该项目还具有向学生传授现代知识的重要教育作用在设计综合和验证的背景下，从决策图到更抽象的字级数据结构的设计表示。