Logic-Layout Co-Synthesis for PTL/CMOS Logic

PTL/CMOS 逻辑的逻辑布局协同综合

• 批准号: 9901254
• 负责人: Maciej Ciesielski
• 金额: $ 25.07万
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-09-15 至 2002-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9901254&HistoricalAwards=false
• 关键词: Logic; Layout; Co; Synthesis; PTL

The goal of this research is to develop a comprehensive methodology forthe synthesis of control dominated random logic circuits, targeting mixedpass-transistor (PTL) and static CMOS logic. Central to this methodologyis the integration of top-down design partitioning and logic synthesiswith bottom-up layout assembly. Specific tasks include: a) algorithmsfor initial Boolean network partitioning; b) novel BDD-based logicdecomposition driven by PTL/CMOS technology requirements; c) circuitsynthesis for mixed CMOS/PTL technology; and d) global level placement andfloorplanning to assume control over the wiring-induced delays in thefinal layout. An experimental synthesis system based on this methodology isnow being developed.

本研究的目标是开发一种综合方法来合成控制主导的随机逻辑电路，针对混合通晶体管 (PTL) 和静态 CMOS 逻辑。该方法的核心是将自上而下的设计划分和逻辑综合与自下而上的布局组装相集成。 具体任务包括： a) 初始布尔网络分区算法； b) 由PTL/CMOS技术要求驱动的新颖的基于BDD的逻辑分解； c) 混合CMOS/PTL技术的电路综合； d) 全局级布局和布局规划，以控制最终布局中布线引起的延迟。目前正在开发基于该方法的实验合成系统。