New Directions in Sequential Synthesis and Optimization

顺序综合和优化的新方向

• 批准号: 9613864
• 负责人: Maciej Ciesielski
• 金额: $ 26.82万
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-01-01 至 2000-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9613864&HistoricalAwards=false
• 关键词: New; Directions; Sequential; Synthesis; Optimization

This research explores a set of techniques for robust logic synthesis tools to support the design automation of high-performance and low-power sequential synchronous circuits. The approach is based on a new concept of logic timing, which combines retiming with logic optimization across register boundaries into a single efficient optimization technique. Also being explored is state encoding for sequential synthesis of circuits specified as finite state machines. The model is based on a controlled reencoding/retiming of the symbolic representation of the state machine represented initially with one-hot code. This facilitates a reliable estimation of circuit cost, such as delay, power, and sequential testability, as a direct function of the encoding. The proposed work is being carried out in collaboration with Advanced Micro Devices, Inc. of Austin, TX.

这项研究探索了一套强大的逻辑综合工具技术，以支持高性能和低功耗时序同步电路的设计自动化。 该方法基于逻辑定时的新概念，它将重定时与跨寄存器边界的逻辑优化结合到单个高效的优化技术中。 还正在探索用于指定为有限状态机的电路的顺序综合的状态编码。 该模型基于最初用 one-hot 代码表示的状态机的符号表示的受控重新编码/重新定时。 这有助于可靠地估计电路成本，例如延迟、功率和顺序可测试性，作为编码的直接函数。 拟议的工作正在与德克萨斯州奥斯汀的 Advanced Micro Devices, Inc. 合作进行。