SBIR Phase I: HW-Accelerated Verification with TestBench Caching and Reduced Design Compilation

SBIR 第一阶段：使用 TestBench 缓存和减少设计编译的硬件加速验证

• 批准号: 0339399
• 负责人: Maciej Ciesielski
• 金额: $ 10万
• 依托单位: LogicMill Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-01-01 至 2004-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0339399&HistoricalAwards=false
• 关键词: SBIR; Phase; HW; Accelerated; Verification

0339399This SBIR Phase I project addresses issues related to verication and debugging of applicationspecic integrated circuits (ASICs) and systems on chip (SOCs) and proposes a novel solution todrastically improve efficiency and performance of design verication. The design vericationalready dominates the overall design development time and negatively impacts the designer pro-ductivity and product's time to market. The proposed method is based on a novel technology, called testbench caching, which reduces by the several orders of magnitude the HW/SW communication overhead. It is combined with the technique that also reduces the need for frequent and time intensive design compilation, and increased signal visibility, essential for fast hardware debugging. Over 100 times improvement is expected w.r.to traditional simulation, and 10-20 times w.r.to traditional simulation acceleration. This project will result in the development of a prototype system to validate the above claims.By accelerating the verication and providing efficient debugging facility the proposed solutionwill substantially shorten time to market for ASIC and SOC designs. Designers productivity willincrease, lowering product development and labor costs. The proposed system methodology willhave a signicant, positive commercial impact and will contribute to the growth of the vericationsystems market.

0339399这个SBIR I期项目解决了与应用程序集成电路（ASIC）和芯片（SOCS）系统的验证和调试有关的问题，并提出了一种新颖的解决方案，以提高设计验证的效率和性能。 设计逐渐准备就在整体设计开发时间中占主导地位，并对设计师的临时性和产品的上市时间产生负面影响。所提出的方法基于一种新型技术，称为TestBench缓存，该技术通过HW/SW通信开销的几个数量级降低。它与该技术还减少了对频繁和时间密集型设计汇编的需求，并提高了信号可见性，这对于快速硬件调试至关重要。预计W.R.到传统模拟的100倍以上，而W.R.到传统的模拟加速度10-20倍。该项目将导致开发原型系统以验证上述主张。通过加速验证并提供有效的调试设施，拟议的解决方案将大大缩短ASIC和SOC设计的市场。设计师的生产力会降低产品的开发和人工成本。拟议的系统方法论将产生显着的积极商业影响，并将有助于序列系统市场的增长。