SHF: Small: Advances in Distributed Spatial-Parallel Event-Driven HDL Simulation

SHF：小型：分布式空间并行事件驱动 HDL 仿真的进展

• 批准号: 1017530
• 负责人: Maciej Ciesielski
• 金额: $ 44.81万
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-09-01 至 2014-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1017530&HistoricalAwards=false
• 关键词: SHF; Small; Advances; Distributed; Spatial

This project proposes an efficient solution to parallel event-driven simulation of digital designs described in a hardware description language (HDL). It is based on a novel concept of spatial parallelism using accurate prediction of input and output signals of individual modules, derived from a model at a higher abstraction level. Using the predicted rather than actual signal values makes it possible to eliminate the need for communication and synchronization between the simulators. The simulation process consists of two phases: 1) Each local simulation is executed using the predicted input, so that no communication and synchronization cost is incurred for exchanging data with other local simulations. Each local simulation stores the results at periodic checkpoints and compares the computed output with the predicted output, to make the correction later, if necessary. 2) If the comparison fails, each local simulation rolls back to the nearest checkpoint to be executed with the actual inputs coming from other modules. This requires exchanging data with other simulations and introduces undesired communication and synchronization overhead. Each local simulation compares the actual input with the predicted input, and if the number of matches exceeds the predetermined threshold, the simulation is switched back to the prediction phase 1. The proposed method is applicable to massively parallel computing platforms and can work with any commercial event-driven HDL simulator.Successful implementation of the proposed method for parallel event-driven HDL simulation will have profound effect on the way dynamic, simulation-based verification is carried out in academia and in industry. It will benefit researchers and all sectors of industry that deal with the design of systems on chip (SoC). It will significantly increase designer productivity in developing and testing complex SoCs, shorten the time to market, lower design development cost and consumer prices. It will fuel the development of other areas of technology, such as multi-core platforms, parallel processors, etc. It will also affect EDA industry developing verification tools ? with new innovative verification tool, automated verification flow and methodology.

该项目为在硬件说明语言（HDL）中描述的数字设计的并行驱动的数字设计模拟提供了有效的解决方案。它基于一种新型的空间并行性概念，该概念是使用单个模块的输入和输出信号的准确预测，该预测是从模型较高的模型中得出的。使用预测的而不是实际的信号值可以消除模拟器之间进行通信和同步的需求。模拟过程由两个阶段组成：1）使用预测输入执行每个局部仿真，因此与其他本地仿真交换数据不会产生通信和同步成本。每个本地模拟将结果存储在定期检查点上，并将计算的输出与预测的输出进行比较，以便在必要时进行校正。 2）如果比较失败，则每个本地模拟都将回到最近的检查点，以执行来自其他模块的实际输入。这需要与其他模拟交换数据，并引入不希望的通信和同步开销。每个本地模拟将实际输入与预测的输入进行比较，如果匹配的数量超过预定的阈值，则将模拟切换回预测阶段1。该方法适用于大规模平行的计算平台，并且可以与任何商业事件驱动的HDL Simulator.SUCCECTENTIND INSUTION型拟合的方法相关的方法，以实现的方式，该方法的实现非常强烈，并实现了事件的实现。基于模拟的验证是在学术界和行业中进行的。它将使研究人员和所有涉及芯片设计设计的行业和所有行业受益。它将显着提高设计人员在开发和测试复杂的SOC，缩短上市时间，降低设计开发成本和消费者价格的时间。它将推动其他技术领域的开发，例如多核平台，并行处理器等。它也会影响EDA行业开发验证工具吗？具有新的创新验证工具，自动验证流量和方法论。