SHF: Small: Advances in Distributed Spatial-Parallel Event-Driven HDL Simulation

SHF：小型：分布式空间并行事件驱动 HDL 仿真的进展

• 批准号: 1017530
• 负责人: Maciej Ciesielski
• 金额: $ 44.81万
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-09-01 至 2014-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1017530&HistoricalAwards=false
• 关键词: SHF; Small; Advances; Distributed; Spatial

This project proposes an efficient solution to parallel event-driven simulation of digital designs described in a hardware description language (HDL). It is based on a novel concept of spatial parallelism using accurate prediction of input and output signals of individual modules, derived from a model at a higher abstraction level. Using the predicted rather than actual signal values makes it possible to eliminate the need for communication and synchronization between the simulators. The simulation process consists of two phases: 1) Each local simulation is executed using the predicted input, so that no communication and synchronization cost is incurred for exchanging data with other local simulations. Each local simulation stores the results at periodic checkpoints and compares the computed output with the predicted output, to make the correction later, if necessary. 2) If the comparison fails, each local simulation rolls back to the nearest checkpoint to be executed with the actual inputs coming from other modules. This requires exchanging data with other simulations and introduces undesired communication and synchronization overhead. Each local simulation compares the actual input with the predicted input, and if the number of matches exceeds the predetermined threshold, the simulation is switched back to the prediction phase 1. The proposed method is applicable to massively parallel computing platforms and can work with any commercial event-driven HDL simulator.Successful implementation of the proposed method for parallel event-driven HDL simulation will have profound effect on the way dynamic, simulation-based verification is carried out in academia and in industry. It will benefit researchers and all sectors of industry that deal with the design of systems on chip (SoC). It will significantly increase designer productivity in developing and testing complex SoCs, shorten the time to market, lower design development cost and consumer prices. It will fuel the development of other areas of technology, such as multi-core platforms, parallel processors, etc. It will also affect EDA industry developing verification tools ? with new innovative verification tool, automated verification flow and methodology.

该项目提出了一种有效的解决方案，用于以硬件描述语言 (HDL) 描述的数字设计的并行事件驱动仿真。它基于空间并行的新颖概念，使用从更高抽象级别的模型派生的各个模块的输入和输出信号的准确预测。使用预测信号值而不是实际信号值可以消除模拟器之间的通信和同步的需要。仿真过程由两个阶段组成：1）每个本地仿真都是使用预测的输入执行的，因此与其他本地仿真交换数据时不会产生通信和同步成本。每个局部模拟都会在定期检查点存储结果，并将计算的输出与预测的输出进行比较，以便在必要时进行稍后的修正。 2) 如果比较失败，则每个本地模拟回滚到最近的检查点，以来自其他模块的实际输入执行。这需要与其他模拟交换数据，并引入不需要的通信和同步开销。每次本地模拟都会将实际输入与预测输入进行比较，如果匹配数量超过预定阈值，则将模拟切换回预测阶段1。该方法适用于大规模并行计算平台，并且可以与任何商业计算平台一起使用事件驱动的 HDL 仿真器。所提出的并行事件驱动 HDL 仿真方法的成功实施将对学术界和工业界进行动态、基于仿真的验证的方式产生深远的影响。它将有利于研究人员和从事片上系统 (SoC) 设计的所有行业部门。它将显着提高设计人员开发和测试复杂SoC的生产力，缩短上市时间，降低设计开发成本和消费者价格。它将推动其他技术领域的发展，例如多核平台、并行处理器等。它也会影响EDA行业开发验证工具？具有新的创新验证工具、自动化验证流程和方法。