Collaborative Research: SHF: Medium: Differentiable Hardware Synthesis
合作研究:SHF:媒介:可微分硬件合成
基本信息
- 批准号:2403135
- 负责人:
- 金额:$ 45万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2024
- 资助国家:美国
- 起止时间:2024-10-01 至 2028-09-30
- 项目状态:未结题
- 来源:
- 关键词:
项目摘要
In the rapidly evolving digital world, creating high-performance and efficient computer hardware is crucial. Electronic design automation (EDA), a process that automates and optimizes the design of hardware, becomes even more critical and challenging with the ever-increasing complexity increases. This project introduces a novel approach to EDA, by solving circuit optimization problems with a blend of formal methods, machine learning, and parallel computing. This proposed research aims to transform the way computer chips are made, making the design process faster, less expensive, and more adaptable. The research findings and tools will be made publicly available to facilitate technology transfers and industry-academia interactions in a multidisciplinary community. The research findings and tools will be made publicly available to support technology transfers and interactions between industry and academia in a multidisciplinary community. This effort will also include active participation in educational and workforce development initiatives, involving high-school students and students from underrepresented groups.In addressing the inherent limitations of existing synthesis solutions, such as unfavorable speed-quality trade-offs and inflexibility in leveraging domain knowledge, the presented research introduces a novel strategy that combines formal techniques with learning-based optimization. Specifically, the research takes a radically different approach by creating differentiable hardware synthesis techniques that are well-suited for heterogeneous computing. The key strategy involves the combination of formal techniques with learning-based optimization, which facilitates efficient global optimization, with or without the need for training data, while taking advantage of the computational power of parallel computing devices like graphics processing units (GPUs). This new approach distinguishes itself from conventional methods by its ability to scale global optimization through parallel computing resources, as well as its potential to combine other machine learning models to enable data-driven optimization via back-propagation. The developed algorithms and software will be made open-source and publicly accessible with comprehensive tutorials and educational materials.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
在快速发展的数字世界中,创建高性能、高效的计算机硬件至关重要。电子设计自动化 (EDA) 是一个自动化和优化硬件设计的过程,随着复杂性的不断增加,它变得更加重要和具有挑战性。该项目引入了一种新颖的 EDA 方法,通过结合形式方法、机器学习和并行计算来解决电路优化问题。这项研究旨在改变计算机芯片的制造方式,使设计过程更快、成本更低、适应性更强。研究结果和工具将公开,以促进多学科社区中的技术转让和产学界互动。研究结果和工具将公开提供,以支持多学科社区中的技术转让以及工业界和学术界之间的互动。这项工作还将包括积极参与教育和劳动力发展计划,让高中生和来自代表性不足群体的学生参与其中。解决现有综合解决方案的固有局限性,例如不利的速度与质量权衡以及利用领域知识的不灵活性,所提出的研究引入了一种将形式技术与基于学习的优化相结合的新颖策略。具体来说,该研究采用了一种截然不同的方法,创建了非常适合异构计算的可微分硬件综合技术。关键策略涉及形式技术与基于学习的优化的结合,这有助于高效的全局优化,无论是否需要训练数据,同时利用图形处理单元(GPU)等并行计算设备的计算能力。这种新方法与传统方法的区别在于它能够通过并行计算资源扩展全局优化,以及结合其他机器学习模型以通过反向传播实现数据驱动优化的潜力。开发的算法和软件将开源并公开,并提供全面的教程和教育材料。该奖项反映了 NSF 的法定使命,并通过使用基金会的智力价值和更广泛的影响审查标准进行评估,被认为值得支持。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Zhiru Zhang其他文献
Building Efficient Deep Neural Networks With Unitary Group Convolutions
使用酉群卷积构建高效的深度神经网络
- DOI:
10.1109/cvpr.2019.01156 - 发表时间:
2018-11-19 - 期刊:
- 影响因子:0
- 作者:
Ritchie Zhao;Yuwei Hu;Jordan Dotzel;Christopher De Sa;Zhiru Zhang - 通讯作者:
Zhiru Zhang
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems
CPU众核异构系统的张量处理框架
- DOI:
10.1109/tcad.2021.3103825 - 发表时间:
2022-06-01 - 期刊:
- 影响因子:2.9
- 作者:
Lin Cheng;Peitian Pan;Zhongyuan Zhao;Krithik Ranjan;Jack Weber;B;hav Veluri;hav;Seyed Borna Ehsani;Max Ruttenberg;Dai Cheol Jung;Preslav Ivanov;D. Richmond;M. Taylor;Zhiru Zhang;C. Batten - 通讯作者:
C. Batten
Image classification with spectral and texture features based on SVM
基于SVM的光谱和纹理特征图像分类
- DOI:
10.1109/geoinformatics.2010.5567663 - 发表时间:
2010-06-18 - 期刊:
- 影响因子:0
- 作者:
Fen Chen;Zhiru Zhang;Dongmei Yan - 通讯作者:
Dongmei Yan
GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation
GLAIVE:图学习辅助指令漏洞估计
- DOI:
10.23919/date51398.2021.9474098 - 发表时间:
2021-02-01 - 期刊:
- 影响因子:0
- 作者:
Jiajia Jiao;D. Pal;Chenhui Deng;Zhiru Zhang - 通讯作者:
Zhiru Zhang
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA
通过激活未使用的触发器来降低 FPGA 中的毛刺功率的行为综合
- DOI:
10.1109/aspdac.2008.4483919 - 发表时间:
2008-01-21 - 期刊:
- 影响因子:0
- 作者:
C. Hsieh;J. Cong;Zhiru Zhang;Shih - 通讯作者:
Shih
Zhiru Zhang的其他文献
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{{ truncateString('Zhiru Zhang', 18)}}的其他基金
Collaborative Research: SHF: Medium: Co-optimizing Spectral Algorithms and Systems for High-Performance Graph Learning
合作研究:SHF:中:协同优化高性能图学习的谱算法和系统
- 批准号:
2212371 - 财政年份:2022
- 资助金额:
$ 45万 - 项目类别:
Continuing Grant
Collaborative Research: FMitF: Track I: DeepSmith: Scheduling with Quality Guarantees for Efficient DNN Model Execution
合作研究:FMitF:第一轨:DeepSmith:为高效 DNN 模型执行提供质量保证的调度
- 批准号:
2019306 - 财政年份:2020
- 资助金额:
$ 45万 - 项目类别:
Standard Grant
SHF: Small: Architectural Synthesis for Programmable Accelerators
SHF:小型:可编程加速器的架构综合
- 批准号:
1909661 - 财政年份:2019
- 资助金额:
$ 45万 - 项目类别:
Standard Grant
CAPA: Collaborative Research: A Multi-Paradigm Programming Infrastructure for Heterogeneous Architectures
CAPA:协作研究:异构架构的多范式编程基础设施
- 批准号:
1723715 - 财政年份:2017
- 资助金额:
$ 45万 - 项目类别:
Standard Grant
STARSS: Small: Automatic Synthesis of Verifiably Secure Hardware Accelerators
STARSS:小型:自动合成可验证安全的硬件加速器
- 批准号:
1618275 - 财政年份:2016
- 资助金额:
$ 45万 - 项目类别:
Standard Grant
CAREER: Synthesizing Highly Efficient Hardware Accelerators for Irregular Programs: A Synergistic Approach
职业:为不规则程序合成高效硬件加速器:一种协同方法
- 批准号:
1453378 - 财政年份:2015
- 资助金额:
$ 45万 - 项目类别:
Continuing Grant
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