SHF: Small: Architectural Synthesis for Programmable Accelerators

SHF：小型：可编程加速器的架构综合

• 批准号: 1909661
• 负责人: Zhiru Zhang
• 金额: $ 48.41万
• 依托单位: Cornell University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-07-01 至 2023-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1909661&HistoricalAwards=false
• 关键词: SHF; Small; Architectural; Synthesis; Programmable

Targeted acceleration of functionality in hardware has shown great promise to bring in orders of magnitude improvement in computational capability for a broad range of applications such as artificial intelligence, autonomous vehicles, web search, and virtual reality. However, it is incredibly time consuming and costly to manually design a hardware accelerator that is both high performance and easily programmable for software. This project aims to develop new design automation framework that can automatically generate a high-quality programmable accelerator from architecture specifications defined in a software program. This project builds on the recent advances in high-level synthesis, which is capable of compiling un-timed behavioral specifications into cycle-accurate register-transfer-level circuits. In contrast to conventional high-level synthesis approaches, the proposed framework generates domain-specific instruction-programmable accelerators as opposed to application-specific fixed-function hardware. This research provides a new class of hardware synthesis infrastructure that integrates domain-specific languages, combinatorial optimization algorithms, and data-driven machine learning capabilities to achieve high quality of results on par with those produced by human experts.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

有针对性地加速硬件功能已显示出巨大的希望，可以为人工智能、自动驾驶汽车、网络搜索和虚拟现实等广泛应用带来计算能力的数量级提高。然而，手动设计既高性能又易于软件编程的硬件加速器非常耗时且成本高昂。该项目旨在开发新的设计自动化框架，该框架可以根据软件程序中定义的架构规范自动生成高质量的可编程加速器。 该项目建立在高级综合的最新进展之上，能够将不定时的行为规范编译成周期精确的寄存器传输级电路。与传统的高级综合方法​​相比，所提出的框架生成特定于领域的指令可编程加速器，而不是特定于应用的固定功能硬件。这项研究提供了一种新型硬件综合基础设施，它集成了特定领域语言、组合优化算法和数据驱动的机器学习功能，以实现与人类专家产生的结果相媲美的高质量结果。该奖项反映了 NSF 的法定使命和通过使用基金会的智力价值和更广泛的影响审查标准进行评估，该项目被认为值得支持。

项目成果

Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC

使用机器学习从痕迹中提取仲裁逻辑：NoC 案例研究

• DOI: 10.1109/dac18074.2021.9586301
• 发表时间: 2021-12
• 期刊: ACM/IEEE Design Automation Conference (DAC
• 作者: Zhou, Yuan;Wang, Hanyu;Yin, Jieming;Zhang, Zhiru
• 通讯作者: Zhang, Zhiru

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product

MatRaptor：一种基于行乘积的稀疏-稀疏矩阵乘法加速器

• DOI: 10.1109/micro50266.2020.00068
• 发表时间: 2020-10
• 期刊: IEEE/ACM International Symposium on Microarchitecture (MICRO-53
• 作者: Srivastava, Nitish;Jin, Hanchen;Liu, Jie;Albonesi, David;Zhang, Zhiru
• 通讯作者: Zhang, Zhiru

HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs

HeteroFlow：用于软件定义 FPGA 的具有解耦数据放置的加速器编程模型

• DOI: 10.1145/3490422.3502369
• 发表时间: 2022-02
• 期刊: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
• 作者: Xiang, Shaojie;Lai, Yi;Zhou, Yuan;Chen, Hongzheng;Zhang, Niansong;Pal, Debjit;Zhang, Zhiru
• 通讯作者: Zhang, Zhiru

GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs

GraphLily：在配备 HBM 的 FPGA 上加速图线性代数

• DOI: 10.1109/iccad51958.2021.9643582
• 发表时间: 2021-11
• 期刊: IEEE/ACM International Conference On Computer Aided Design (ICCAD
• 作者: Hu, Yuwei;Du, Yixiao;Ustun, Ecenur;Zhang, Zhiru
• 通讯作者: Zhang, Zhiru

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV

使用 HLS 在配备 HBM 的 FPGA 上实现高性能稀疏线性代数：SpMV 案例研究

• DOI: 10.1145/3490422.3502368
• 发表时间: 2022-02
• 期刊: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
• 作者: Du, Yixiao;Hu, Yuwei;Zhou, Zhongchun;Zhang, Zhiru
• 通讯作者: Zhang, Zhiru