Collaborative Research: An Effective and Efficient Low-Cost Alternate to Cell Aware Test Generation for Cell Internal Defects

协作研究：针对电池内部缺陷的电池感知测试生成有效且高效的低成本替代方案

• 批准号: 2331003
• 负责人: Adit Singh
• 金额: $ 30万
• 依托单位: Auburn University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2331003&HistoricalAwards=false
• 关键词: Collaborative; Research; Effective; Efficient; Low

Society’s growing reliance on intelligent electronic systems risks significant disruption and loss from integrated circuit failure. Mitigating this threat requires building electronic systems that have been extensively tested to ensure that they are fully functional and defect-free. Modern integrated circuits contain billions of transistors that makes a complete exhaustive test of circuit functionality impractical and infeasible. Such tests are generated in practice, by considering the impact of likely manufacturing defects such as shorts and opens at various circuit locations, and developing a set of input test patterns whose correct binary output is altered by the existence of any targeted fault, identifying a bad integrated circuit. However, it is not practical to model and target all possible malfunctions in a large circuit, especially those that employ deeply scaled technologies, low supply voltages and high clock speeds. As a consequence, some faulty circuits inevitably escape post-manufacture testing because of incomplete test coverage and cause integrated circuit failure when deployed in operation. The goal of this research is to develop better and significantly more cost-effective test methods for state-of-the-art integrated circuits that can significantly impact the affordability and reliability of future computing systems that are increasingly pervasive in day-to-day societal applications and critical for national defense. The project will also help train new students in this strategic area, consistent with recent priorities for US leadership in semiconductor manufacturing. Traditional test methods for integrated circuits generate test inputs that explicitly detect faulty behavior only at the terminals of the standard cell building blocks and the interconnections between these cells. It is now widely known that detection of defective devices can be enhanced by considering defects within the cell circuitry as well. To do this, currently, faults are injected one at a time at likely defect locations in the cell layout, followed by exhaustive circuit simulation of all possible input patterns to obtain cell level tests. The generated tests are then delivered to cells embedded in logic circuitry using circuit-level test generation algorithms. This has major drawbacks. First, it is expensive to characterize the full range of resistive defects at every possible location in large cells using exhaustive circuit simulation. In practice, only ideal shorts and opens are simulated, leading to test escapes. Second, this does not consider the significant impact of a timing delay in one cell on the delays of other interconnected cells. Third, existing test generation techniques such as cell aware test, can increase test size and application time by greater than fivefold. To address these issues, this project seeks to develop a new testing methodology that avoids exhaustive simulation, but instead uses analytical reasoning to generate tests for cell internal defects. Algorithms based on this analytic approach can generate compact tests that cover defects spanning large resistance ranges without the need for repeated simulations. Additionally, the delay impact of a single defect that affects multiple cells can also be effectively captured, minimizing the escape of timing faults.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

社会对智能电子系统的日益依赖有可能导致综合电路故障造成重大破坏和损失。缓解这种威胁需要进行广泛测试的电子系统，以确保它们功能齐全且无缺陷。现代集成电路包含数十亿个晶体管，可以对电路功能进行完整的详尽测试，不切实际且不可行。通过考虑可能在各个电路位置打开等可能的制造缺陷的影响，并开发一组输入测试模式，从而在实践中生成了此类测试，这些缺陷会因存在任何目标故障而改变了正确的二进制输出，从而确定了不良的集成电路。但是，在大型电路中建模和针对所有可能的故障是不切实际的，尤其是那些员工深度缩放技术，低电源电压和高时钟速度的速度。结果，由于不完整的测试覆盖范围，某些故障电路不可避免地逃脱了生产后测试，并在运行中部署时会导致综合电路故障。这项研究的目的是为最先进的综合电路开发更好，更明显的具有成本效益的测试方法，这些电路可能会严重影响未来计算系统的可用性和可靠性，这些计算系统在日常社交应用中越来越普遍，并且对国防部进行至关重要。该项目还将帮助培训该战略领域的新学生，这与美国半导体制造业领导者的最新优先事项一致。集成电路的传统测试方法生成的测试输入，这些输入仅在标准细胞构建块的终端和这些单元之间的互连处明确检测出故障行为。现在众所周知，通过考虑细胞电路中的缺陷，可以增强故障设备的检测。为此，目前，在细胞布局中可能的缺陷位置一次注射故障，然后对所有可能的输入模式进行详尽的电路模拟，以获得细胞水平测试。然后，使用电路级测试生成算法将生成的测试传递到嵌入在逻辑电​​路中的单元。这有主要的缺点。首先，使用详尽的电路模拟来表征大单元中每个可能位置的全部电阻缺陷范围很昂贵。实际上，仅模拟理想的短裤和打开，导致测试逃逸。其次，这并不认为一个细胞中的正时延迟对其他相互连接的细胞的延迟的显着影响。第三，现有的测试生成技术（例如细胞意识测试）可以将测试尺寸和应用时间增加超过五倍。为了解决这些问题，该项目试图开发一种避免详尽模拟的新测试方法，而是使用分析推理来生成细胞内部缺陷的测试。基于这种分析方法的算法可以生成紧凑的测试，该测试涵盖了跨越大电阻范围的缺陷，而无需重复模拟。此外，也可以有效地捕获影响多个单元的单个缺陷的延迟影响，从而最大程度地减少了正时故障的逃脱。该奖项反映了NSF的法定使命，并通过使用基金会的知识分子优点和更广泛的影响评估标准来评估我们被认为是诚实的支持。