Silicon Calibrated Scan Based Timing Tests for Delay Defect Detection

用于延迟缺陷检测的基于硅校准扫描的时序测试

• 批准号: 0811454
• 负责人: Adit Singh
• 金额: $ 35万
• 依托单位: Auburn University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-01 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811454&HistoricalAwards=false
• 关键词: Silicon; Calibrated; Scan; Based; Timing

Project ID: CCF - 0811454Title: eSilicon Calibrated Scan Based Timing Tests for Delay Defect DetectionPI name: Singh, Adit D. Institution: Auburn University, AlabamaAbstractMicroscopic manufacturing flaws, such as the localized narrowing of interconnection lines, via voids, and pin holes in insulating gate oxide, are a major reliability concern in nanometer digital integrated circuit technologies. Such defects are difficult to detect during production testing because they often do not cause catastrophic malfunction in the circuit; instead, circuit switching delays may be marginally increased along the signal paths containing the defect. Since a complex chip contains billions of circuit paths of varying lengths, and circuit clock timing is designed to accommodate the longest path delay, small delay defects on short paths can remain hidden within circuit timing slacks during post manufacturing testing. However, such defects can often cause errors under worse case operating conditions or degrade further under the stress of field operation to cause early life reliability failure. These small delay defects can potentially be detected through more aggressive timing tests, using faster than rated clock frequencies, to capture and expose any erroneous response due to the excessive delays along short paths. This requires the use of the scan design-for-test methodology which provides full access to the internal flip-flops in sequential designs, and can thereby allow circuit timing to be observed for single cycle operation. Scan delay tests check if signal propagation delays along the targeted paths in the circuit, activated by two vector delay test patterns, fall within the applied ?launch? to ?capture? clock period. However, because single cycle scan tests operate the circuit in a manner which is different from normal multi-cycle sequential operation, there is increasing evidence that the observed circuit timing may not reflect true circuit delays in normal continuous functional operation. Factors such as power supply noise, coupling and cross talk from abnormal switching activity, variations in die thermal profile, and ?clock stretching? can all significantly impact scan test timing. Normal manufacturing process variations further add to these test timing uncertainties, making the detection of small delay defects extremely challenging. This research takes the view that it may be impractical to observe true circuit functional timing with sufficient accuracy using a surrogate scan based timing test to reliably detect small delay defects. Instead, such defects are better detected by identifying abnormal switching delays (timing anomalies) through a comparison of timing test results from a matched population of parts. Here the scan tests are not used to test circuit timing against a fixed rated clock (e.g. as required for speed binning), but only to identify anomalous parts that display abnormal delays relative to the statistical norm for the population. Critically, this relative rather than absolute timing evaluation eliminates the need for the scan timing tests to accurately match functional timing. The impact of common mode factors such as power supply and coupling noise, clock stretching, etc. is factored out by the comparison test. Non-functional test inputs can also be used by the test, with multiple fast clocks, to achieve high coverage of small delay defects, even on short paths. Preliminary research has experimentally shown that if test responses from adjacent die are compared, delay defects of size less than 5% of the critical path can be reliably detected. This research is developing and evaluating a number of new methodologies to make such silicon ?calibrated? scan delay testing practical and commercially attractive. The new delay test methodologies will be evaluated using specially designed test chips. A longer term goal of the proposed research is to carry out experimental studies, in partnership with industry, to validate the methodologies developed on volume production parts. This research project will help improve the research capabilities of Alabama, an EPSCoR state. Results from the research will also be incorporated in advanced courses taught by the PI, both at Auburn and off campus, through the IEEE Test Technology Education Program. The PI works closely with the Historically Black Tuskegee University located near Auburn, including cooperating on an ongoing joint NSF Computing Research Infrastructure (CRI) grant in the VLSI testing area. Tuskegee students take graduate courses at Auburn University, and some are jointly advised by Auburn faculty. Tuskegee Ph.D. students, who have taken graduate courses with the PI, will be encouraged to participate in this research. This will further strengthen the research interaction between Auburn and Tuskegee, which is helping to attract minority U.S. citizens to graduate studies the computing field.

项目 ID：CCF - 0811454 标题：用于延迟缺陷检测的基于 eSilicon 校准扫描的时序测试 PI 名称：Singh，Adit D。机构：阿拉巴马州奥本大学摘要微观制造缺陷，例如互连线的局部变窄、通孔空隙和绝缘中的针孔栅极氧化物是纳米数字集成电路技术中主要的可靠性问题。此类缺陷在生产测试期间很难检测到，因为它们通常不会导致电路发生灾难性故障；相反，沿着包含缺陷的信号路径，电路开关延迟可能会略微增加。由于复杂的芯片包含数十亿条不同长度的电路路径，并且电路时钟时序被设计为适应最长的路径延迟，因此在制造后测试期间，短路径上的小延迟缺陷可能仍然隐藏在电路时序松弛中。然而，此类缺陷通常会在最恶劣的操作条件下导致错误，或者在现场操作的压力下进一步退化，从而导致早期寿命可靠性故障。这些小的延迟缺陷可以通过更积极的时序测试来检测，使用比额定时钟频率更快的时钟频率，以捕获和暴露由于短路径上的过度延迟而导致的任何错误响应。这需要使用扫描测试设计方法，该方法在顺序设计中提供对内部触发器的完全访问，从而可以观察单周期操作的电路时序。扫描延迟测试检查由两个矢量延迟测试模式激活的沿电路中目标路径的信号传播延迟是否落在所应用的“启动”范围内。捕捉？时钟周期。然而，由于单周期扫描测试以不同于正常多周期顺序操作的方式操作电路，因此越来越多的证据表明观察到的电路时序可能无法反映正常连续功能操作中的真实电路延迟。诸如电源噪声、异常开关活动引起的耦合和串扰、芯片热分布变化以及“时钟拉伸”等因素。都会显着影响扫描测试时间。正常的制造工艺变化进一步增加了这些测试时序的不确定性，使得检测小延迟缺陷变得极具挑战性。本研究认为，使用基于代理扫描的时序测试来可靠地检测小延迟缺陷，以足够的精度观察真实的电路功能时序可能是不切实际的。相反，通过比较匹配的零件群的时序测试结果来识别异常开关延迟（时序异常），可以更好地检测此类缺陷。这里，扫描测试不用于针对固定额定时钟测试电路时序（例如，速度分级所需的），而仅用于识别相对于总体统计规范显示异常延迟的异常部分。至关重要的是，这种相对而非绝对时序评估消除了扫描时序测试精确匹配功能时序的需要。通过对比测试，排除了电源和耦合噪声、时钟拉伸等共模因素的影响。测试还可以使用非功能测试输入，通过多个快速时钟，实现小延迟缺陷的高覆盖率，即使在短路径上也是如此。初步研究表明，如果比较相邻芯片的测试响应，则可以可靠地检测到尺寸小于关键路径 5% 的延迟缺陷。这项研究正在开发和评估一些新方法来使这种硅“校准”。扫描延迟测试实用且具有商业吸引力。新的延迟测试方法将使用专门设计的测试芯片进行评估。拟议研究的长期目标是与工业界合作进行实验研究，以验证在批量生产零件上开发的方法。该研究项目将有助于提高 EPSCoR 州阿拉巴马州的研究能力。研究结果还将被纳入 PI 通过 IEEE 测试技术教育计划在奥本和校外教授的高级课程中。该 PI 与奥本附近的历史黑人塔斯基吉大学密切合作，包括在 VLSI 测试领域与 NSF 计算研究基础设施 (CRI) 联合资助项目进行合作。塔斯基吉学生在奥本大学攻读研究生课程，其中一些课程由奥本大学教师共同指导。塔斯基吉博士将鼓励已与 PI 一起修读研究生课程的学生参与这项研究。这将进一步加强奥本大学和塔斯基吉大学之间的研究互动，这有助于吸引美国少数族裔公民攻读计算机领域的研究生。