EHCS: Dynamic Vertically Integrated Power-Performance-Reliability Modulation in Embedded Digital Signal Processors

EHCS：嵌入式数字信号处理器中的动态垂直集成功率性能可靠性调制

• 批准号: 0834620
• 负责人: Adit Singh
• 金额: $ 22万
• 依托单位: Auburn University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-15 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0834620&HistoricalAwards=false
• 关键词: EHCS; Dynamic; Vertically; Integrated; Power

Serious new technical challenges are barriers to advances in microelectronics technology as technology scaling comes up against fundamental limits of material properties and lithography. Large process variations and other random performance and power constraining imperfections are now being observed as microelectronic devices are scaled down to atomic dimensions. This requires that module level performance in electronic designs be pessimistically guardbanded to ensure proper overall system level functionality, forcing systems to operate at performance levels far below the inherent capability of the underlying design fabric. In addition, embedded DSP systems must be designed to work under worst case operating conditions resulting from ill-conditioned input signals. Wider guardbands from increasing performance and input signal variability in future technologies can negate most of the performance benefits of scaling, stalling a key payoff from Moore?s Law for embedded systems. In such an environment, introduction of new scaled devices will be cost-effective only if the guardbands can be controlled down to acceptable margins, despite the presence of these uncertainties. This remains a major unsolved challenge, especially for embedded DSP processors that must be concurrently optimized for system level power, performance and reliability. To address these problems, this project is developing the concept of test, diagnosis and continuous signal monitoring enabled dynamic circuit-architecture-algorithm co-modulation (or co-tuning) for both static (procees) and dynamic (input signal) uncertainties. Under this new design paradigm, feedback driven reconfiguration control mechanisms involving circuitry and software (?tuning knobs?) are designed into the IC to support power-performance trade-off and reliability recovery post manufacture. The research pursues vertically integrated circuit-architecture-algorithm tuning methods that offer 10X benefits over optimizations performed at a single level of the design hierarchy. The diagnostic information generated is used to dynamically optimize (post-manufacture) individual module level behavior to optimize system level performance, power and reliability metrics via specially designed hardware and software control mechanisms. In this way, each instantiation of a design adapts to the maximum performance, power, and reliability levels it is capable of in the presence of process variations and adverse operating conditions. Graduate students working on the project receive a unique kind of training in this multidisciplinary research, which together the fields of digital design and test, control systems, embedded digital signal processing architectures, and algorithms. The students participate in summer internship programs with industry. Through joint efforts at Georgia Tech, Auburn University, and Tuskegee University, this project also actively supports the goals of recruiting more U.S. citizens, women and minorities to graduate programs.

严重的新技术挑战是微电学技术进步的障碍，因为技术扩展符合材料属性和光刻的基本限制。现在，随着微电器设备的缩放到原子维度，现在正在观察到较大的过程变化以及其他随机性能和功率约束缺陷。 这就要求对电子设计中的模块级别的性能进行悲观的护罩，以确保适当的整体系统级功能，从而迫使系统在性能水平上运行远低于基础设计结构的固有能力。 此外，嵌入式DSP系统必须设计为在不良条件输入信号导致的最坏情况下工作。未来技术中的性能和输入信号变异性的增加，较宽的后卫队伍可以消除扩展的大多数性能优势，从而使摩尔法律从嵌入式系统中获得关键的回报。在这样的环境中，只有在存在这些不确定性的情况下，只有将护栏控制到可接受的利润率时，才能将新扩展设备的引入具有成本效益。这仍然是一个主要的未解决的挑战，特别是对于嵌入式DSP处理器，必须同时对系统级别的功率，性能和可靠性进行优化。为了解决这些问题，该项目正在开发测试，诊断和连续信号监控的概念，启用了动态电路 - 构造 - 叠加 - 算法共调制（或共同调节），均可用于静态（procees）和动态（输入信号）不确定性。在这个新的设计范式下，涉及电路和软件的反馈驱动的重新配置控制机制（？调整旋钮？）是在IC中设计的，以支持Power-Cormer-crounterance Realight offermance折衷和可靠性恢复后制造后制造。该研究追求垂直集成的电路结构 - 算法调整方法，这些方法比在设计层次结构的单个级别进行的优化提供了10倍的好处。生成的诊断信息用于动态优化（生产后）单个模块级别行为，以通过专门设计的硬件和软件控制机制优化系统级别的性能，功率和可靠性指标。通过这种方式，设计的每个实例化都适应了过程变化和不良操作条件的最大性能，功率和可靠性水平。从事该项目的研究生接受了这项多学科研究的独特培训，这些培训在数字设计和测试，控制系统，嵌入式数字信号处理体系结构和算法的领域共同培训。学生们参加了行业的暑期实习计划。通过在佐治亚理工学院，奥本大学和塔斯基吉大学的联合努力，该项目还积极支持招募更多美国公民，妇女和少数民族来研究生课程的目标。