ITR: Built-In Test of High Speed/RF Mixed Signal Electronics

ITR：高速/射频混合信号电子设备的内置测试

• 批准号: 0325426
• 负责人: Adit Singh
• 金额: $ 23.35万
• 依托单位: Auburn University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-08-15 至 2007-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0325426&HistoricalAwards=false
• 关键词: ITR; Built; Test; Speed; RF

PROJECT TITLE: ITR: Built-In Test of High Speed/RF Mixed Signal ElectronicsPROPOSAL NO.: 0325555INSTITUTION: Georgia Inst. Technology, GAPRINCIPAL INVESTIGATOR: Abhijit Chatterjee (lead PI)PROPOSAL NO.: 0325371INSTITUTION: U. Texas, Austin, TXPRINCIPAL INVESTIGATOR: Jacob Abrahams (coPI)PROPOSAL NO.: 0325426INSTITUTION: Auburn University, AlabamaPRINCIPAL INVESTIGATOR: Adit D. Singh (coPI)PROPOSAL NO.: 0325340INSTITUTION: University of FloridaPRINCIPAL INVESTIGATOR:William R. Eisenstadt (coPI)ABSTRACT:In the recent past, there has been a tremendous surge in the wired communications/wireless/high-speed IC manufacturing sector. While the design community has pushed the design envelope far into the future, the test barriers have not kept pace with the test requirements of high speed, integrated wireless and wired communications designs. Every IC that is manufactured, needs to be tested against its design specifications before shipment to the customer. As the speeds of these ICs increase, so do the requirements of the testers needed to test these ICs in manufacturing production. High-speed testers above 2 GHz are prohibitively expensive. Consequently, for speeds beyond a few GHz (2 - 25 GHz), built-in test (BIT) of high-speed/RF systems is a very attractive solution. Built-in test involves incorporation of test circuitry in the IC itself to facilitate the manufacturing test process. In this way, many of the test functions are performed "on-chip," alleviating the need for a high-speed (expensive) external tester. Since test cost is projected to escalate to about 40% of the total manufacturing cost of complex communications ICs in the near future, the use of built-in test is expected to significantly impact the cost of the manufactured ICs themselves and the ability of companies to compete in the marketplace.The core concept behind the proposed built-in test methodology is easy to follow. Instead of directly measuring the high-speed test specifications of the IC-under-test, a new paradigm for BIT of high-speed/RF circuits using alternate tests is proposed. Alternate tests are compact tests that are much more simpler to run than the original specification tests but contain as much information (or more) about the performance of the circuit-under-test as the original tests themselves. Furthermore, it is possible to design these tests so that pass-fail decisions can be made, based on analysis of analog signals using analog circuitry. In this way, two problems are solved: (a) that of being able to measure complex high-speed test specifications using simple on-chip test resources and a low-cost external tester, and (b) that of being able to analyze very high-speed signals ( 2 Ghz) without the need to digitize them (such digitizers are not available or are very expensive at these frequencies). The proposed work is interdisciplinary and will involve the use of concepts from computer algorithms, analog/RF circuit design, mathematics and statistics and fundamental electrical engineering and device physics.

项目名称：ITR：高速/射频混合信号电子的内置测试提案编号：0325555机构：佐治亚研究所。技术，GA 首席研究员：Abhijit Chatterjee（首席 PI）提案编号：0325371 机构：美国德克萨斯州奥斯汀，TX 首席研究员：Jacob Abrahams (coPI) 提案编号：0325426 机构：阿拉巴马州奥本大学首席研究员：Adit D. Singh (coPI) 提案编号：0325340 机构：佛罗里达大学 主要调查员：William R. Eisenstadt (coPI) 摘要：近年来，有线通信/无线/高速 IC 制造领域出现了巨大的增长。尽管设计界已将设计范围推向了遥远的未来，但测试障碍却未能跟上高速、集成无线和有线通信设计的测试要求。每个制造出来的 IC 在运送给客户之前都需要根据其设计规范进行测试。随着这些 IC 速度的提高，对在制造生产中测试这些 IC 所需的测试仪的要求也随之提高。 2 GHz 以上的高速测试仪非常昂贵。因此，对于超过几 GHz (2 - 25 GHz) 的速度，高速/RF 系统的内置测试 (BI​​T) 是一个非常有吸引力的解决方案。内置测试涉及将测试电路合并到 IC 本身中，以促进制造测试过程。通过这种方式，许多测试功能都是在“片上”执行的，从而减少了对高速（昂贵）外部测试仪的需求。由于测试成本预计在不久的将来将上升到复杂通信 IC 总制造成本的 40% 左右，因此内置测试的使用预计将显着影响制造 IC 本身的成本以及公司的能力。在市场上竞争。所提议的内置测试方法背后的核心概念很容易理解。提出了一种使用交替测试的高速/射频电路 BIT 的新范例，而不是直接测量被测 IC 的高速测试规范。替代测试是紧凑的测试，其运行比原始规范测试简单得多，但包含与原始测试本身一样多（或更多）的有关被测电路性能的信息。此外，可以设计这些测试，以便基于使用模拟电路对模拟信号的分析来做出通过/失败决策。这样，解决了两个问题：(a)能够使用简单的片上测试资源和低成本的外部测试器来测量复杂的高速测试规范，以及(b)能够分析非常复杂的高速测试规范。高速信号 (2 Ghz)，无需对其进行数字化（此类数字化仪在这些频率下不可用或非常昂贵）。拟议的工作是跨学科的，将涉及计算机算法、模拟/射频电路设计、数学和统计学以及基础电气工程和设备物理概念的使用。