FET:Small: An Integrated Unipolar-0.5T0.5R RRAM Crossbar Array for Neuromorphic Computing

FET:小型:用于神经形态计算的集成单极 0.5T0.5R RRAM 交叉阵列

基本信息

  • 批准号:
    2132820
  • 负责人:
  • 金额:
    $ 50万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2021
  • 资助国家:
    美国
  • 起止时间:
    2021-08-15 至 2024-07-31
  • 项目状态:
    已结题

项目摘要

The processing capabilities of the human brain are unparalleled compared to what is achievable with conventional computing techniques, particularly for applications targeted toward pattern recognition, and needs dedicated hardware to be emulated. Neuromorphic (NM) computing hardware, which aims to mimic these neuro-architectural aspects of the human brain by having the memory- and processing-centers co-located (compute-in-memory), can deliver processing and computations on an energy scale that is orders of magnitude more efficient than the conventional von-Neumann architecture where data are transferred between separate memory and processing elements. Therefore, NM computing can enable significant computational advances for a variety of real-world applications. The compute-in-memory hardware is typically implemented using a crossbar array layout of resistive random-access memory (RRAM) devices, where each memory device is connected in series with a control transistor, in what is commonly referred to as a one-transistor one-resistor (1T1R) cell format. Although this format ensures the memory devices work reliably and efficiently, it increases the device count and circuit area. The PI has recently demonstrated a novel "0.5T0.5R" memory cell architecture where a control device - a transistor - and a memory element - a RRAM - are integrated into a single hybrid device by judicious use of two-dimensional (2D) materials with resulting substantial improvements in the scaling, density, and device/circuit performance. The three-year project involves the design, fabrication, and characterization of crossbar arrays of these devices to implement compute-in-memory hardware, thereby enabling demonstration of large-scale NM computing circuits. The application space of NM computing is targeted towards both machine learning and pattern recognition and can be used in a multitude of real-world applications not limited to self-driving cars and big data, thereby enabling a much broader scientific impact. Moreover, significant improvements in the energy-efficiency of NM and in-memory computing paradigms will enable their wide-scale deployment and enable computing hardware to keep pace with the rapid growth in data intensive applications in spite of CMOS technology scaling limitations. Thus, the project is expected to have wide implications for the semiconductor and electronics industries. Moreover, the PI will use various well established educational platforms to disseminate the research results and to make them available to a wide range of users. The overall project also ties research to education at all levels involving K-12, undergraduates, graduates, and minorities, partly via participation in programs designed by education professionals, besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.This project involves the conceptualization, design optimization, and hardware demonstration of novel and energy-efficient neuromorphic/in-memory computing circuits enabled by innovative large-scale crossbar array implementation of a novel 0.5T0.5R memory device. Experimental work is being carried out with close modeling and simulation support to optimize the device and array design. More specifically, development of compact models with the aid of numerical and ab-initio simulations to help in device optimization and developing neural learning algorithms, to be subsequently implemented in the crossbar array, is being carried out in tandem. The interdisciplinary nature of the research project, spanning fundamental 2D materials science, device design, and nano-fabrication techniques, as well as theoretical simulations and system architecture design, ensures that the proposed research ideas are feasible and tailored to deliver optimal neural learning and inference objectives. Significant improvements over recently demonstrated NM computing devices are proposed, employing large-area 2D materials synthesis techniques and configuring the hybrid device to provide further scalability and ease of energy-efficiently addressing array elements. Finally, hardware neural tasks pertaining to real-world applications of pattern recognition, cybersecurity, and implementing physically unclonable functions are being demonstrated. The successful completion of this project is intended to advance the development of a revolutionary new class of NM computing systems that efficiently emulate biological information processing.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
与传统计算技术相比,人脑的处理能力是无与伦比的,特别是针对模式识别的应用程序,并且需要模拟专用硬件。神经形态(NM)计算硬件旨在通过将内存和处理中心放在同一位置(内存中计算)来模仿人脑的这些神经结构方面,可以在能量规模上提供处理和计算,比传统的冯诺依曼架构效率高出几个数量级,传统的冯诺依曼架构中数据在单独的内存和处理元件之间传输。因此,NM 计算可以为各种实际应用带来显着的计算进步。内存计算硬件通常使用电阻式随机存取存储器 (RRAM) 器件的交叉阵列布局来实现,其中每个存储器器件与控制晶体管串联,通常称为单晶体管单电阻 (1T1R) 单元格式。虽然这种格式可以确保存储器件可靠且高效地工作,但它增加了器件数量和电路面积。 PI 最近展示了一种新颖的“0.5T0.5R”存储单元架构,其中控制器件(晶体管)和存储元件(RRAM)通过明智地使用二维 (2D) 材料集成到单个混合器件中从而在尺寸、密度和器件/电路性能方面得到显着改进。这个为期三年的项目涉及这些设备的交叉阵列的设计、制造和表征,以实现内存计算硬件,从而实现大规模 NM 计算电路的演示。 NM 计算的应用空间针对机器学习和模式识别,可用于多种实际应用,而不仅限于自动驾驶汽车和大数据,从而产生更广泛的科学影响。此外,NM 和内存计算范式的能源效率的显着提高将使其能够大规模部署,并使计算硬件能够跟上数据密集型应用的快速增长,尽管 CMOS 技术的扩展受到限制。因此,该项目预计将对半导体和电子行业产生广泛影响。此外,PI将利用各种完善的教育平台来传播研究成果并将其提供给广泛的用户。整个项目还将研究与涉及 K-12、本科生、研究生和少数族裔的各级教育联系起来,部分通过参与教育专业人员设计的项目,此外还重点关注纳米科学和工程领域代表性不足的群体的招募和保留。该项目涉及通过新型 0.5T0.5R 存储器件的创新型大规模交叉阵列实现,实现新型节能神经形态/内存计算电路的概念化、设计优化和硬件演示。实验工作正在紧密的建模和仿真支持下进行,以优化器件和阵列设计。更具体地说,正在同时进行借助数值和从头算仿真的紧凑模型的开发,以帮助设备优化和开发神经学习算法,随后将在交叉开关阵列中实现。该研究项目的跨学科性质,涵盖基础二维材料科学、器件设计和纳米制造技术,以及理论模拟和系统架构设计,确保所提出的研究想法是可行的,并且经过量身定制,以提供最佳的神经学习和推理目标。提出了对最近演示的 NM 计算设备的重大改进,采用大面积 2D 材料合成技术并配置混合设备,以提供进一步的可扩展性和易于节能寻址阵列元素。最后,正在演示与模式识别、网络安全和实现物理不可克隆功能的实际应用相关的硬件神经任务。该项目的成功完成旨在推动革命性的新型 NM 计算系统的开发,该系统可有效模拟生物信息处理。该奖项反映了 NSF 的法定使命,并通过利用基金会的智力优势和更广泛的评估进行评估,认为值得支持。影响审查标准。

项目成果

期刊论文数量(1)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Two-dimensional materials enabled next-generation low-energy compute and connectivity
  • DOI:
    10.1557/s43577-022-00270-0
  • 发表时间:
    2021-12
  • 期刊:
  • 影响因子:
    5
  • 作者:
    Arnab K. Pal;Kunjesh Agashiwala;Junkai Jiang;Dujiao Zhang;Tanmay Chavan;Ankit Kumar;C. Yeh;W. Cao;K. Banerjee
  • 通讯作者:
    Arnab K. Pal;Kunjesh Agashiwala;Junkai Jiang;Dujiao Zhang;Tanmay Chavan;Ankit Kumar;C. Yeh;W. Cao;K. Banerjee
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Kaustav Banerjee其他文献

Localized heating effects and scaling of sub-0.18 micron CMOS devices
0.18 微米以下 CMOS 器件的局部热效应和缩放
University of California, Santa Barbara
加州大学圣塔芭芭拉分校
  • DOI:
  • 发表时间:
    2007
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Kaustav Banerjee
  • 通讯作者:
    Kaustav Banerjee
Electrical characterization of back-gated and top-gated germanium-core/silicon-shell nanowire field-effect transistors
背栅和顶栅锗核/硅壳纳米线场效应晶体管的电气特性
  • DOI:
  • 发表时间:
    2016
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Marolop Dapot Krisman Simanullang,Gde Bimananda Mahardika Wisna,Koichi Usami;Wei Cao;Kaustav Banerjee;and Shunri Oda
  • 通讯作者:
    and Shunri Oda
An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs
由 2D-TMD 隧道 FET 支持的神经拟态计算超节能硬件平台
  • DOI:
    10.1038/s41467-024-46397-3
  • 发表时间:
    2024
  • 期刊:
  • 影响因子:
    16.6
  • 作者:
    Arnab Pal;Zichun Chai;Junkai Jiang;W. Cao;Mike Davies;Vivek De;Kaustav Banerjee
  • 通讯作者:
    Kaustav Banerjee
One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across math xmlns="http://www.w3.org/1998/Math/MathML" display="inline" overflow="scroll">msub>mrow> mi>Mo/mi>mi mathvariant="normal">S/mi>/mrow>
一维边缘接触到二维过渡金属二硫化物:揭示肖特基势垒各向异性在数学电荷传输中的作用 xmlns="http://www.w3.org/1998/Math/MathML" display="inline
  • DOI:
  • 发表时间:
  • 期刊:
  • 影响因子:
    0
  • 作者:
    K. Parto;Arnab Pal;Tanmay Chavan;Kunjesh Agashiwala;Chao;W. Cao;Kaustav Banerjee
  • 通讯作者:
    Kaustav Banerjee

Kaustav Banerjee的其他文献

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{{ truncateString('Kaustav Banerjee', 18)}}的其他基金

EAGER: Exploration of 3D-Transistors with 2D-TMDs for Ultimate Miniaturization
EAGER:探索具有 2D-TMD 的 3D 晶体管以实现终极小型化
  • 批准号:
    2332341
  • 财政年份:
    2023
  • 资助金额:
    $ 50万
  • 项目类别:
    Standard Grant
NSF:EAGER: 2D Layered Heterostructure based Tunnel Field-Effect Transistors (TFETs) and Circuits
NSF:EAGER:基于 2D 分层异质结构的隧道场效应晶体管 (TFET) 和电路
  • 批准号:
    1550230
  • 财政年份:
    2015
  • 资助金额:
    $ 50万
  • 项目类别:
    Standard Grant
SHF: Medium: A Collaborative Framework for Developing Green Electronics for Next-Generation Computing Applications
SHF:Medium:为下一代计算应用开发绿色电子的协作框架
  • 批准号:
    1162633
  • 财政年份:
    2012
  • 资助金额:
    $ 50万
  • 项目类别:
    Continuing Grant
SHF:Small: A CAD Framework for Coupled Electrical-Thermal Modeling of Interconnects in 3D Integrated Circuits
SHF:Small:3D 集成电路互连电热耦合建模的 CAD 框架
  • 批准号:
    0917385
  • 财政年份:
    2009
  • 资助金额:
    $ 50万
  • 项目类别:
    Standard Grant
CPA-DA-T: A Collaborative Framework for Design and Fabrication of Metallic Carbon Nanotube based Interconnect Structures for VLSI Circuits and Systems Applications
CPA-DA-T:用于设计和制造用于超大规模集成电路和系统应用的基于金属碳纳米管的互连结构的协作框架
  • 批准号:
    0811880
  • 财政年份:
    2008
  • 资助金额:
    $ 50万
  • 项目类别:
    Standard Grant
A CAD Framework for Multiscale Electrothermal Modeling and Simulation of Non-Classical CMOS Devices
非经典 CMOS 器件多尺度电热建模和仿真的 CAD 框架
  • 批准号:
    0541465
  • 财政年份:
    2006
  • 资助金额:
    $ 50万
  • 项目类别:
    Continuing Grant

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FET: Small: An Integrated Framework for the Optimal Control of Open Quantum Systems --- Theory, Quantum Algorithms, and Applications
FET:小型:开放量子系统最优控制的集成框架 --- 理论、量子算法和应用
  • 批准号:
    2312456
  • 财政年份:
    2023
  • 资助金额:
    $ 50万
  • 项目类别:
    Standard Grant
FET: III: Small: Innovative Approaches for Bias Correction and Systems-level Analysis in Integrated Multi-omics Data
FET:III:小型:集成多组学数据中的偏差校正和系统级分析的创新方法
  • 批准号:
    2203236
  • 财政年份:
    2022
  • 资助金额:
    $ 50万
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FET: Small: Design Optimization of Silicon Photonic Integrated Circuits under Fabrication Process Variations
FET:小型:制造工艺变化下硅光子集成电路的设计优化
  • 批准号:
    2006788
  • 财政年份:
    2020
  • 资助金额:
    $ 50万
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FET: Small: Collaborative Research: Integrated Spintronic Synapses and Neurons for Neuromorphic Computing Circuits - I(SNC)^2
FET:小型:协作研究:用于神经形态计算电路的集成自旋电子突触和神经元 - I(SNC)^2
  • 批准号:
    1910800
  • 财政年份:
    2019
  • 资助金额:
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FET: Small: Spectrally Efficient High-dimensional Quantum Communications in an Integrated Quantum Photonic Platform
FET:小型:集成量子光子平台中的光谱效率高维量子通信
  • 批准号:
    1907918
  • 财政年份:
    2019
  • 资助金额:
    $ 50万
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