SHF:Small: A CAD Framework for Coupled Electrical-Thermal Modeling of Interconnects in 3D Integrated Circuits

SHF:Small：3D 集成电路互连电热耦合建模的 CAD 框架

• 批准号: 0917385
• 负责人: Kaustav Banerjee
• 金额: $ 45万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-08-01 至 2013-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0917385&HistoricalAwards=false
• 关键词: SHF; Small; CAD; Framework; Coupled

The semiconductor industry is at an interesting crossroads, where traditional scaling of CMOS devices is beginning to confront significant challenges that are threatening to derail the more than four-decades old Moore?s law. 3D integrated circuits (3D ICs) offer an exciting alternative, where in lieu of scaling, continuous increase in functionality, performance and integration density can be sustained indefinitely by stacking semiconductor layers on top of each other in a ?monolithic? manner. A 3D IC is comprised of two or more active (semiconducting) layers that have been thinned, bonded and interconnected using special vertical wires drilled through the active layers known as ?Through Silicon Vias (TSV)?. When TSVs (10-100 micrometer long) are used to replace the longest (several millimeters) on-chip horizontal wires as well as some chip-to-chip connections (on printed circuit boards), significant reduction in wire delay and chip power dissipation can be achieved. Moreover, 3D ICs also offer the most promising platform to implement ?More-than-Moore? technologies, bringing heterogeneous materials (Silicon, III-V semiconductors, Graphene, etc) and technologies (memory, logic, RF, mixed-signal, MEMS, optoelectronics, etc) on a single chip. However, modeling and analysis of interconnects in 3D ICs present new and significantly more complex problems. In contrast with traditional interconnects, the modeling of high aspect-ratio TSVs embedded in a semiconducting material with non-uniform currents in the third dimension, and electromagnetic coupling of interconnects with multiple conductive substrates at high-frequencies, constitute new challenges for design and design-automation methods. Furthermore, the high power-density in 3D ICs due to multiple active layers and their limited heat removal options give rise to large three-dimensional thermal gradients, making it important to consider the coupling between thermal and electromagnetic properties of interconnects and the surrounding media. Finally, the need for accuracy is accompanied by the computational challenge of handling a large number of coupled interconnects at the system level, as 3D integration further exacerbates the size of the interconnect problem.This project will develop the necessary foundations for coupled electrical-thermal modeling and analysis of interconnects and passives in 3D ICs, considering the electromagnetic coupling of general 3D interconnects with multiple substrates at ultra-high frequencies as well as the physical attributes of high aspect-ratio TSVs (including geometry, material and density), using thermally-aware and inherently efficient techniques to enable full-chip modeling of the large system of interconnects. The overall program also ties research to education at all levels besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.

半导体行业正处于一个有趣的十字路口，传统的 CMOS 器件微缩技术开始面临重大挑战，这些挑战有可能破坏已有四十多年历史的摩尔定律。 3D 集成电路 (3D IC) 提供了一种令人兴奋的替代方案，通过将半导体层堆叠在“单片”中，可以无限期地持续增加功能、性能和集成密度，以代替缩放。方式。 3D IC 由两个或多个有源（半导体）层组成，这些层已使用穿过有源层（称为“硅通孔 (TSV)”）的特殊垂直导线进行减薄、粘合和互连。 当使用 TSV（10-100 微米长）取代最长（几毫米）的片上水平导线以及某些芯片到芯片的连接（印刷电路板上）时，可显着降低导线延迟和芯片功耗可以实现。此外，3D IC 还提供了最有前途的平台来实现“超越摩尔定律”。技术，将异构材料（硅、III-V 半导体、石墨烯等）和技术（存储器、逻辑、射频、混合信号、MEMS、光电子等）集成到单个芯片上。 然而，3D IC 中互连的建模和分析提出了新的且更加复杂的问题。与传统互连相比，嵌入在三维非均匀电流的半导体材料中的高深宽比 TSV 的建模，以及高频下互连与多个导电基板的电磁耦合，对设计和设计提出了新的挑战-自动化方法。 此外，由于多个有源层及其有限的散热选项，3D IC 中的高功率密度会产生大的三维热梯度，因此必须考虑互连和周围介质的热和电磁特性之间的耦合。最后，对准确性的需求伴随着在系统级处理大量耦合互连的计算挑战，因为 3D 集成进一步加剧了互连问题的规模。该项目将为耦合电热建模奠定必要的基础3D IC 中的互连和无源器件分析，考虑到超高频下通用 3D 互连与多个基板的电磁耦合以及高深宽比 TSV 的物理属性（包括几何、材料和密度），使用热感知和固有高效技术来实现大型互连系统的全芯片建模。除了关注纳米科学和工程领域代表性不足的群体的招募和保留之外，整个计划还将研究与各级教育联系起来。