A CAD Framework for Multiscale Electrothermal Modeling and Simulation of Non-Classical CMOS Devices

非经典 CMOS 器件多尺度电热建模和仿真的 CAD 框架

• 批准号: 0541465
• 负责人: Kaustav Banerjee
• 金额: --
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-06-01 至 2009-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541465&HistoricalAwards=false
• 关键词: CAD; Framework; Multiscale; Electrothermal; Modeling

0541465Banerjee, KaustavU of Cal Santa BarbaraA CAD Framework for Multiscale Electrothermal Modeling and Simulation of Non-Classical CMOS DevicesAs scaling of CMOS devices continues unabated beyond the 90 nm node, a number of critical challenges including severe short-channel effects, increasing leakage currents and power dissipation are accelerating the introduction of new materials and device structures to extend the lifetime of CMOS down to, and perhaps beyond the 22 nm node. These devices are classified as non-classical CMOS and include strained-Si, ultra-thin body Silicon-on-Insulator (UTB-SOI), double-gate (such as FinFETs) and multi-gate devices. While these device structures seek to address the above mentioned scaling challenges, thermal management in these ultra scaled devices is an increasing concern made worse by the introduction of materials with poorer thermal conductivity (SOI, SiGe) and the physical confinement of the device geometries. Moreover, for device geometries where the mean free path of the phonons are comparable to (or larger than) the device size (channel length), classical drift-diffusion theory fails to accurately predict the temperature profile in the channel region of the transistors. At present, CAD tools that are widely used for device level electrothermal simulations, use drift-diffusion or hydrodynamic models and energy-balance equations assuming local thermodynamic equilibrium and therefore do not account for these effects, thereby compromising the performance and reliability of integrated circuits based on these devices. Moreover, there is no well defined methodology that combines electrothermal models at different length scales (as needed for a CMOS transistor) and subsequently generates accurate compact models to allow fast electrothermal simulations. Additionally, lack of thermal management in these emerging CMOS devices can also lead to significant increase in reliability problems such as electrostatic discharge (ESD), which is known to be the largest single cause of all IC failures in the semiconductor industry. Hence, there is an imminent need for developing suitable CAD framework for accurate multi-scale electrothermal modeling and simulation, in order to understand the impact of thermal effects on the electrical characteristics of these non-classical devices and subsequently on their circuit performance and reliability. The framework is also critical for optimizing the design of these devices and to understand various electrical-thermal tradeoffs.The PI plans to develop the necessary CAD framework to enable multi-scale electrothermal modeling and simulation capabilities for ultra-scaled non-classical CMOS devices. The research involves a unique approach that combines a small-scale sub-continuum electrothermal simulation methodology involving the electron-phonon Boltzmann Transport Equations (BTE) with a macro-scale heat-diffusion based methodology. The small-scale simulations are necessary to account for the non-locality of phonon transport near the high electric field (drain) region of the transistor and involve self-consistent solutions of the electron-BTE and the phonon-BTE to generate accurate heat flux and thermal profile along the channel of the device. Next, by coupling together the results of these simulations with the ones from classical heat-diffusion approach (for other areas of the transistors) the PI will develop accurate physical as well as compact models for various electrothermal quantities including thermal resistance, thermal capacitance and thermal time constant as a function of device materials, process and bias conditions, and device geometry. These compact models will then be used to carry out fast steady-state and transient electrothermal simulations using SPICE and thereby analyze and optimize various transistor architectures. Most importantly, since performance and power dissipation are critically dependent on the thermal profile, the electrothermal CAD framework will be used to design thermally-aware circuits so that maximum benefit can be derived from them and various electrical-thermal tradeoffs can be carried out. Additionally, the PI will study implications for ESD protection circuitsunderstand electrothermal behavior under high-current conditions and optimize device design for improving ESD reliability. The overall program also ties research to education at all levels (K-12, undergraduate, graduate, continuing-ed) partly via participation in programs designed by education professionals. As an affiliated faculty of the California NanoSystems Institute (CNSI), the PI plans to participate in various outreach activities sponsored by the CNSI as well as those offered by the Materials Research Lab (MRL) and the Nanotech (NNIN) at UCSB including the student and teacher research training internship programs. Additionally, the project provides a substantial focus on recruitment and retention of underrepresented groups into nanoscience and engineering.

0541465Banerjee, KaustavU of Cal Santa Barbara用于非经典 CMOS 器件多尺度电热建模和仿真的 CAD 框架随着 CMOS 器件的微缩在 90 nm 节点之后继续有增无减，许多关键挑战包括严重的短沟道效应、增加的漏电流和功率耗散正在加速新材料和器件结构的引入，以将 CMOS 的寿命延长至甚至超过 22 nm 节点。 这些器件被归类为非经典 CMOS，包括应变硅、超薄体绝缘体上硅 (UTB-SOI)、双栅极（例如 FinFET）和多栅极器件。虽然这些器件结构试图解决上述缩放挑战，但这些超大规模器件中的热管理日益受到关注，由于引入导热性较差的材料（SOI、SiGe）和器件几何形状的物理限制，问题变得更加严重。 此外，对于声子的平均自由程与器件尺寸（沟道长度）相当（或大于）的器件几何形状，经典的漂移扩散理论无法准确预测晶体管沟道区域的温度分布。目前，广泛用于器件级电热仿真的 CAD 工具使用漂移扩散或流体动力学模型以及假设局部热力学平衡的能量平衡方程，因此没有考虑这些效应，从而损害了基于集成电路的性能和可靠性。在这些设备上。此外，还没有明确定义的方法来结合不同长度尺度的电热模型（根据 CMOS 晶体管的需要）并随后生成精确的紧凑模型以允许快速电热模拟。此外，这些新兴 CMOS 器件缺乏热管理也会导致可靠性问题显着增加，例如静电放电 (ESD)，众所周知，静电放电是半导体行业所有 IC 故障的最大单一原因。因此，迫切需要开发合适的 CAD 框架来进行精确的多尺度电热建模和仿真，以了解热效应对这些非经典器件的电气特性及其电路性能和可靠性的影响。 该框架对于优化这些器件的设计以及了解各种电热权衡也至关重要。PI 计划开发必要的 CAD 框架，以实现超大规模非经典 CMOS 器件的多尺度电热建模和仿真功能。 该研究采用了一种独特的方法，将涉及电子声子玻尔兹曼输运方程（BTE）的小规模亚连续电热模拟方法与基于宏观热扩散的方法相结合。 小规模模拟对于解释晶体管高电场（漏极）区域附近声子传输的非局域性是必要的，并且涉及电子 BTE 和声子 BTE 的自洽解以生成精确的热通量以及沿器件通道的热分布。接下来，通过将这些模拟的结果与经典热扩散方法（用于晶体管的其他区域）的结果结合在一起，PI 将为各种电热量（包括热阻、热容和热）开发精确的物理和紧凑模型。时间常数是器件材料、工艺和偏置条件以及器件几何形状的函数。 然后，这些紧凑模型将用于使用 SPICE 进行快速稳态和瞬态电热仿真，从而分析和优化各种晶体管架构。最重要的是，由于性能和功耗很大程度上取决于热分布，因此电热 CAD 框架将用于设计热感知电路，以便从中获得最大收益，并可以进行各种电热权衡。 此外，PI 将研究 ESD 保护电路的影响，了解高电流条件下的电热行为，并优化器件设计以提高 ESD 可靠性。 整个计划还将研究与各级教育（K-12、本科生、研究生、继续教育）联系起来，部分通过参与教育专业人士设计的计划来实现。作为加州纳米系统研究所 (CNSI) 的附属教员，PI 计划参加 CNSI 赞助的各种外展活动以及 UCSB 材料研究实验室 (MRL) 和纳米技术 (NNIN) 提供的活动，包括学生和教师研究培训实习计划。此外，该项目还重点关注纳米科学和工程领域代表性不足群体的招募和保留。