CPA-DA-T: A Collaborative Framework for Design and Fabrication of Metallic Carbon Nanotube based Interconnect Structures for VLSI Circuits and Systems Applications

CPA-DA-T：用于设计和制造用于超大规模集成电路和系统应用的基于金属碳纳米管的互连结构的协作框架

• 批准号: 0811880
• 负责人: Kaustav Banerjee
• 金额: $ 100万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-01 至 2013-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811880&HistoricalAwards=false
• 关键词: CPA; DA; Collaborative; Framework; Design

Proposal ID: 0811880PI Name: Kaustav BanerjeeInstitution: University of California-Santa BarbaraTitle: A Collaborative Framework for Design and Fabrication of Metallic Carbon Nanotube based Interconnect Structures for VLSI Circuits and Systems Applications ABSTRACTThe semiconductor industry is confronting an acute problem in the interconnect area due to the limited current carrying capability of copper wires, which are presently used to connect billions of transistors in every integrated circuit (IC) including microprocessors that are vital for information transmission, processing and storage. As IC feature sizes continue to be scaled below 45 nanometer, copper wires exhibit significant ?size effects? resulting in a sharp rise in their resistivity, which, in turn, has adverse impact both on their performance as well as reliability---in the form of current carrying capacity. This limitation of copper interconnects has been recently highlighted by various leading semiconductor companies around the world as well as in the International Technology Roadmap for Semiconductors (ITRS), and threatens to slow down or even stall the traditional growth of the semiconductor and related industries. Hence, it is critical to identify and develop new interconnect solutions. Carbon nanotubes, tiny nanostructures 80,000 times narrower than a human hair, are known to have amazing electrical, thermal and mechanical properties, and can potentially address the challenges faced by copper and thereby extend the lifetime of ?electrical interconnects?. Most of these outstanding properties arise from the ?low-dimensionality? of CNTs---since they are essentially 1-dimensional structures. The investigators seek to, for the first time, understand how these tiny structures can be efficiently integrated into microprocessors and other circuitry to address the dire need for faster and more reliable on-chip wiring. The CNT interconnect structures also offer exciting prospects for design of ultra high-density energy storage elements (such as capacitors and inductors), as well as various system-level architectural innovations. This collaborative four-year project brings together a team of scientists and engineers for addressing the key scientific and engineering challenges associated with the design and fabrication of CNT interconnect structures for various circuits and systems applications. The investigators employ an interdisciplinary approach that combines innovative process technology and circuit/system architecture development supported by rigorous modeling, analysis, and metrology techniques. This presents an outstanding opportunity to truly demonstrate the prospects of CNTs in overcoming one of the major limitations of nanometer scale ICs, and is expected to have wide implications for the semiconductor industry. This research will help scaling of CMOS circuits to its ultimate limits and also open new opportunities in mixed-signal, analog and radio-frequency (RF) signal processing applications as well as in 3-dimensional integrated circuit design, thereby maintaining U.S. competitiveness in the worldwide semiconductor market. Broader impact of the research includes emerging off-chip applications of carbon nanotubes as ?solder bumps? and also as an excellent thermal interface material for heat removal from chips and printed circuit boards. The overall program also ties research to education at all levels (K-12, undergraduate, graduate, continuing-education) partly via participation in programs designed by education professionals, besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.

提案 ID：0811880PI 名称：Kaustav Banerjee 机构：加州大学圣巴巴拉分校 标题：用于 VLSI 电路和系统应用的基于金属碳纳米管的互连结构设计和制造的协作框架 摘要 由于以下原因，半导体行业在互连领域面临着严重的问题：铜线的载流能力有限，目前铜线用于连接每个集成电路 (IC) 中的数十亿个晶体管，包括微处理器对于信息传输、处理和存储至关重要。 随着 IC 特征尺寸继续缩小到 45 纳米以下，铜线表现出显着的“尺寸效应”。导致其电阻率急剧上升，进而对其性能和可靠性（以载流能力的形式）产生不利影响。最近，全球多家领先的半导体公司以及国际半导体技术路线图（ITRS）都强调了铜互连的这种局限性，并有可能减缓甚至阻碍半导体及相关行业的传统增长。 因此，识别和开发新的互连解决方案至关重要。碳纳米管是一种比人类头发丝细 80,000 倍的微小纳米结构，具有惊人的电学、热学和机械性能，可以解决铜面临的挑战，从而延长“电气互连”的使用寿命。大多数这些突出的特性都源于“低维”。碳纳米管——因为它们本质上是一维结构。 研究人员首次试图了解如何将这些微小结构有效地集成到微处理器和其他电路中，以满足对更快、更可靠的片上布线的迫切需求。 CNT互连结构还为超高密度储能元件（例如电容器和电感器）的设计以及各种系统级架构创新提供了令人兴奋的前景。 这个为期四年的合作项目汇集了一组科学家和工程师，致力于解决与各种电路和系统应用的 CNT 互连结构的设计和制造相关的关键科学和工程挑战。研究人员采用跨学科方法，将创新工艺技术和电路/系统架构开发相结合，并由严格的建模、分析和计量技术支持。这提供了一个绝佳的机会，可以真正展示碳纳米管在克服纳米级集成电路的主要限制之一方面的前景，并有望对半导体行业产生广泛的影响。 这项研究将有助于将 CMOS 电路缩小到其极限，并为混合信号、模拟和射频 (RF) 信号处理应用以及 3 维集成电路设计开辟新的机遇，从而保持美国在该领域的竞争力。全球半导体市场。 该研究的更广泛影响包括碳纳米管作为“焊料凸块”的新兴片外应用。也可作为出色的热界面材料，用于芯片和印刷电路板的散热。整个计划还将研究与各级教育（K-12、本科生、研究生、继续教育）联系起来，部分通过参与教育专业人员设计的计划，此外还重点关注纳米科学和工程领域代表性不足群体的招募和保留。