SHF: Medium: Collaborative Research: Photonic Neural Network Accelerators for Energy-efficient Heterogeneous Multicore Architectures

SHF：媒介：协作研究：用于节能异构多核架构的光子神经网络加速器

基本信息

批准号：
1901165
负责人：
Ahmed Louri
金额：
$ 60万
依托单位：
George Washington University
依托单位国家：
美国
项目类别：
Continuing Grant
财政年份：
2019
资助国家：
美国
起止时间：
2019-08-01 至 2024-07-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1901165&HistoricalAwards=false
关键词：
SHF Medium Collaborative Research Photonic

项目摘要

Deep learning architectures such as convolutional neural networks and recurrent neural networks have achieved unprecedented, sometimes super-human accuracy on many modern applications in artificial intelligence, such as image classification and speech recognition. Power dissipation is however a major concern in these energy-hungry machine-learning architectures, and decreasing it requires designs that provide a more energy-efficient combination of hardware and machine-learning algorithms. There is an increased emphasis to leverage parallelism and specialization to improve performance and energy efficiency. To dramatically reduce power consumption, silicon photonics has been proposed to improve performance-per-Watt compared to electrical implementation.This project leverages photonic technology and heterogeneous multicores for the design of deep-neural network accelerators that improve parallelism, concurrency, energy efficiency and scalability in various machine-learning applications. The first task of the project is concerned with the characterization and identification of photonic devices that can implement accelerator functionalities such as multiply-and-accumulate, summation, and other arithmetic operations. The characterized devices are then inserted into single-layer and multi-layer photonic topologies for implementing accelerator functionality. The second task of the project implements various types of deep-learning architectures on the proposed photonic neural network accelerator to maximize the gains offered by the photonic technology. The third task of the project builds an extensive simulation and modeling infrastructure that combines the photonic technology, network architectures, accelerator functionality, and machine-learning algorithms developed in the previous two steps, in order to validate the significant reduction in energy consumption enabled by the photonic neural-network accelerator.The proposed research bridges a very important gap between photonic technology, hardware architecture, and machine learning. As such, and due to its cross-cutting nature, it is expected to have far-reaching impacts on the design of next-generation multicore architectures. It will foster new research directions in several areas, spanning computer architecture, optical technology, machine learning algorithms and applications. The research will also play a major role in education by integrating discovery with teaching and training. All the research findings and simulation toolkits will be disseminated to the community via conference and journal publications, and a dedicated website.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

卷积神经网络和循环神经网络等深度学习架构在人工智能的许多现代应用（例如图像分类和语音识别）中实现了前所未有的、有时甚至超人类的准确性。然而，功耗是这些高耗能机器学习架构中的一个主要问题，要降低功耗就需要提供更节能的硬件和机器学习算法组合的设计。人们越来越重视利用并行性和专业化来提高性能和能源效率。为了大幅降低功耗，与电气实现相比，硅光子学被提议提高每瓦性能。该项目利用光子技术和异构多核来设计深度神经网络加速器，以提高并行性、并发性、能源效率和可扩展性在各种机器学习应用中。该项目的第一个任务涉及光子器件的表征和识别，这些器件可以实现乘法累加、求和和其他算术运算等加速器功能。然后将表征的器件插入单层和多层光子拓扑中以实现加速器功能。该项目的第二个任务是在所提出的光子神经网络加速器上实现各种类型的深度学习架构，以最大限度地提高光子技术提供的收益。该项目的第三个任务是建立一个广泛的模拟和建模基础设施，结合前两个步骤中开发的光子技术、网络架构、加速器功能和机器学习算法，以验证通过该技术实现的能耗显着降低。光子神经网络加速器。所提出的研究弥合了光子技术、硬件架构和机器学习之间的一个非常重要的差距。因此，由于其交叉性质，预计将对下一代多核架构的设计产生深远的影响。它将在计算机架构、光学技术、机器学习算法和应用等多个领域培育新的研究方向。该研究还将发现与教学和培训相结合，在教育中发挥重要作用。所有研究成果和模拟工具包都将通过会议和期刊出版物以及专门网站向社区传播。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

期刊论文数量（14）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning

通过强化学习进行硬件级线程迁移以减少片上数据移动

DOI：
10.1109/tcad.2020.3012650
发表时间：
2020-11
期刊：
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
影响因子：
2.9
作者：
Fettes, Quintin;Karanth, Avinash;Bunescu, Razvan;Louri, Ahmed;Shiflett, Kyle
通讯作者：
Shiflett, Kyle

An Approximate Communication Framework for Network-on-Chips

片上网络的近似通信框架

DOI：
10.1109/tpds.2020.2968068
发表时间：
2020-06
期刊：
IEEE Transactions on Parallel and Distributed Systems
影响因子：
5.3
作者：
Chen, Yuechen;Louri, Ahmed
通讯作者：
Louri, Ahmed

Exploiting Wireless Technology for Energy-Efficient Accelerators With Multiple Dataflows and Precision

利用无线技术实现具有多个数据流和精度的节能加速器

DOI：
10.1109/tcsi.2022.3166752
发表时间：
2022-07
期刊：
IEEE Transactions on Circuits and Systems I: Regular Papers
影响因子：
0
作者：
Liu, Siqin;Canan, Talha Furkan;Chenji, Harshavardhan;Laha, Soumyasanta;Kaya, Savas;Karanth, Avinash
通讯作者：
Karanth, Avinash

SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based Accelerator With Photonic Interconnects for CNN Inference

SPRINT：高性能、节能且可扩展的基于 Chiplet 的加速器，具有用于 CNN 推理的光子互连