Collaborative Research: CSR: Small: Cross-layer learning-based Energy-Efficient and Resilient NoC design for Multicore Systems

协作研究：CSR：小型：基于跨层学习的多核系统节能和弹性 NoC 设计

• 批准号: 2321224
• 负责人: Ahmed Louri
• 金额: $ 37.5万
• 依托单位: George Washington University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2321224&HistoricalAwards=false
• 关键词: Collaborative; Research; CSR; Small; Cross

The proliferation of multiple cores on the chip has signaled the advent of communication-centric, rather than computation-centric systems. Consequently, the design of low latency, high bandwidth, power-efficient, and reliable Network-on-Chips (NoCs) is proving to be one of the most critical challenges to achieving the performance potential of future multicore systems. However, as multicores are facilitating an enormous integration capacity, rapid transistor scaling has led to a steady degradation of the device and circuit reliability: unpredictable device behavior will undeniably increase and will result in a significant increase in faults (both permanent and transient), and hardware failures. The ramifications for the NoC are immense: a single fault in the NoC may paralyze the working of the entire chip. While considerable efforts are undertaken to tackle the reliability challenge of NoCs, most current solutions concentrate on local optimizations within the entire NoC abstractions (e.g., circuit, message, and network layers). These solutions tend to possess limited knowledge of the overall system and are therefore reactive in behavior, making worst-case assumptions and overprovisioning, and as a result, they introduce significant power, area, and performance overheads while not completely solving the reliability challenge.This research project tackles the critical NoC reliability challenge by developing a comprehensive, cooperative, and adaptive multi-layer approach for designing reliable NoCs from fault-susceptible components, with globally-optimized power, performance, and costs. To achieve this research goal, this project is organized into four interrelated research tasks. First, this research project conducts a comprehensive study of the fundamental mechanisms that underlie the reliability issues across NoC abstractions. A detailed analysis of the dynamic interactions of NoC abstractions and design trade-offs. Second, the research project develops a cross-layer NoC architecture for resilient on-chip communication with machine-learning-based optimization. Third, this research project aims to incorporate the application layer and off-chip communications and develops a holistic design framework that can automatically capture and adapt to the various computation and communication requirements of different applications with optimized performance, power, and reliability. Finally, the project evaluates the designed framework by developing a cycle-accurate simulation framework and an FPGA prototype. This project will significantly advance the fundamental understanding of the interplay between the NoC and the rest of the components on the chip (cores, memory, etc.) as well as design tradeoffs between performance, power, reliability, and cost in future massively defective nanometer technologies. The developed NoC framework will benefit future multi-core architectures and computing systems with system-level performance and reliability improvements.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

芯片上多核的激增标志着以通信为中心而非以计算为中心的系统的出现。因此，低延迟、高带宽、节能且可靠的片上网络 (NoC) 的设计被证明是实现未来多核系统性能潜力的最关键挑战之一。然而，随着多核正在促进巨大的集成能力，晶体管的快速缩放导致器件和电路可靠性的稳步下降：不可否认的器件行为将不可避免地增加，并将导致故障（永久性和瞬态）的显着增加，并且硬件故障。 NoC 的影响是巨大的：NoC 中的单个故障可能会导致整个芯片的工作瘫痪。尽管为解决 NoC 的可靠性挑战付出了巨大的努力，但当前大多数解决方案都集中在整个 NoC 抽象（例如电路、消息和网络层）内的局部优化。这些解决方案往往对整个系统的了解有限，因此在行为上是被动的，做出最坏情况的假设和过度配置，因此，它们会带来巨大的功耗、面积和性能开销，同时无法完全解决可靠性挑战。该研究项目通过开发一种全面、协作和自适应的多层方法来解决关键的 NoC 可靠性挑战，该方法可利用易受故障影响的组件设计可靠的 NoC，并具有全局优化的功耗、性能和成本。为了实现这一研究目标，该项目分为四个相互关联的研究任务。首先，该研究项目对 NoC 抽象的可靠性问题的基本机制进行了全面的研究。详细分析 NoC 抽象和设计权衡的动态交互。其次，该研究项目开发了一种跨层 NoC 架构，通过基于机器学习的优化实现弹性片上通信。第三，该研究项目旨在整合应用层和片外通信，并开发一个整体设计框架，可以自动捕获和适应不同应用的各种计算和通信需求，并优化性能、功耗和可靠性。最后，该项目通过开发周期精确的仿真框架和 FPGA 原型来评估设计的框架。该项目将显着促进对片上网络 (NoC) 与芯片上其他组件（核心、内存等）之间相互作用的基本理解，以及未来存在严重缺陷的纳米技术中性能、功耗、可靠性和成本之间的设计权衡。技术。所开发的NoC框架将通过系统级性能和可靠性改进使未来的多核架构和计算系统受益。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。