SHF: Medium: Collaborative Research: Scaling On-chip Networks to 1000-core Systems using Heterogeneous Emerging Interconnect Technologies

SHF：中：协作研究：使用异构新兴互连技术将片上网络扩展到 1000 核系统

• 批准号: 1513923
• 负责人: Ahmed Louri
• 金额: $ 48万
• 依托单位: University of Arizona
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-08-01 至 2015-10-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1513923&HistoricalAwards=false
• 关键词: SHF; Medium; Collaborative; Research; Scaling

Power dissipation has become a fundamental barrier to scaling computing performance across all platforms from handheld, embedded systems, to laptops, to servers to data centers. Technology scaling down to the sub-nanometer regime has aided the growth in transistors per chip that has made multi-core architectures a power-efficient approach to harnessing parallelism and improving performance. The computing capabilities of these multi-core architectures can be unleashed only if the underlying Network-on-Chip (NoC) connecting the cores can provide the required bandwidth within the power budget of the chip. However, the design of power-efficient, low-latency and high-bandwidth NoCs using traditional metallic interconnects that can scale to 1000 cores and beyond, is proving to be a significant challenge of enormous proportions. Research has shown that emerging technologies such as photonics and wireless have the potential to alleviate the critical bandwidth, power, and latency challenges of future NoCs. However, hybrid NoC designs taking advantages of both photonics and wireless technologies have not been explored. This research proposes to lay the groundwork for completely re-thinking the NoC design and proposes to explore heterogeneity of emerging interconnect technology for designing performance scalable, and power-efficient NoCs. The overall objective is to combine multiple technologies to achieve our challenging goals of (1) scalability to 1000 cores, (2) power efficiency of at least a 50% power reduction as compared to the state-of-the-art metallic interconnects, and (3) high bandwidth and low latency across a wide variety of applications. First, at the architecture level, optics will be deployed for short-range ( 100 cores) to improve local communication and wireless for long-range communication in order to scale the number of cores to 1000 by providing sufficient global bandwidth. Second, at the circuit level, hybrid transceiver architectures will be explored to integrate novel ultra-low power wireless circuits based on SiGe/BiCMOS technology with optical waveguides and ring-resonators to provide the large bandwidth desired for kilo-core designs. Furthermore, wireless communication requirements will be addressed by designing mm-wave/THz frequency broadband and directional antennas based on advanced 3D printing technology. This proposal describes a transformative and viable approach combining technology, architecture, algorithms and applications research for designing scalable and energy-efficient NoCs. The cross-cutting nature of this research will foster new research directions in several areas, spanning technology/energy-aware NoC design, novel computer architectures, and cutting-edge modeling and simulations tools for emerging technologies.

功耗已成为扩展所有平台（从手持式、嵌入式系统、笔记本电脑、服务器到数据中心）计算性能的基本障碍。技术缩小到亚纳米范围有助于增加每个芯片的晶体管数量，从而使多核架构成为利用并行性和提高性能的节能方法。只有连接核心的底层片上网络 (NoC) 能够在芯片的功率预算内提供所需的带宽，才能释放这些多核架构的计算能力。然而，事实证明，使用可扩展到 1000 个核心甚至更多的传统金属互连来设计高能效、低延迟和高带宽 NoC 是一项巨大的挑战。研究表明，光子学和无线等新兴技术有潜力缓解未来片上网络面临的关键带宽、功耗和延迟挑战。然而，尚未探索利用光子学和无线技术的混合 NoC 设计。本研究旨在为彻底重新思考 NoC 设计奠定基础，并建议探索新兴互连技术的异构性，以设计性能可扩展且高能效的 NoC。总体目标是结合多种技术来实现我们具有挑战性的目标：(1) 可扩展至 1000 个内核，(2) 与最先进的金属互连相比，功率效率至少降低 50%，以及(3) 跨多种应用的高带宽和低延迟。首先，在架构层面，将部署光学器件用于短距离（100个核心），以改善本地通信，并采用无线技术进行远程通信，以便通过提供足够的全局带宽将核心数量扩展到1000个。其次，在电路层面，将探索混合收发器架构，将基于 SiGe/BiCMOS 技术的新型超低功耗无线电路与光波导和环形谐振器集成，以提供千核设计所需的大带宽。此外，无线通信需求将通过基于先进3D打印技术设计毫米波/太赫兹频率宽带和定向天线来满足。该提案描述了一种结合技术、架构、算法和应用研究的变革性可行方法，用于设计可扩展且节能的片上网络。这项研究的跨领域性质将在多个领域培育新的研究方向，涵盖技术/能源感知 NoC 设计、新颖的计算机架构以及新兴技术的尖端建模和仿真工具。