SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures Optimized for Energy, Performance and Reliability

SHF：中：协作研究：支持机器学习的片上网络架构，针对能源、性能和可靠性进行了优化

基本信息

批准号：
1702980
负责人：
Ahmed Louri
金额：
$ 45万
依托单位：
George Washington University
依托单位国家：
美国
项目类别：
Continuing Grant
财政年份：
2017
资助国家：
美国
起止时间：
2017-06-01 至 2023-05-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1702980&HistoricalAwards=false
关键词：
SHF Medium Collaborative Research Machine

项目摘要

Network-on-Chip (NoC) architectures have emerged as the prevailing on-chip communication fabric for multicores and Chip Multiprocessors (CMPs). However, as NoC architectures are scaled, they face serious challenges. A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing, energy efficient and fault tolerant techniques available to NoC designers and the large design space that must be navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. This research proposes a new cross-layer, cross-cutting methodology spanning circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient, reliable and scalable NoCs. This research will result in (1) novel cross-layer design techniques that take a holistic approach of simultaneously reducing power consumption, while still achieving reliability and performance goals for NoCs, (2) a fundamental understanding of the use of hardware-amenable ML for NoC design optimization, (3) software and hardware techniques for monitoring and collecting critical data and key design parameters during network execution to optimize NoC design, and (4) modeling and simulation tools that will improve the architecture community?s design methodologies for evaluating scalable NoCs. The proposed research bridges a very important gap between hardware architects who design power management and fault tolerant techniques at the circuit and architecture level and machine learning scientists who develop predictive and optimization techniques. Due to its cross-cutting nature, the proposed research has the potential to significantly transform the design of next-generation CMPs and System-on-Chips (SoCs) where complex decisions have to be made that affect the power, performance and reliability. The research will also play a major role in education by integrating discovery with teaching and training. The PIs are committed and will continue to expand on outreach activities as part of the proposed project by making the necessary efforts to attract and train minority students in this field.

片上网络 (NoC) 架构已成为多核和片上多处理器 (CMP) 的主流片上通信结构。然而，随着 NoC 架构的扩展，它们面临着严峻的挑战。当今解决优化 NoC 架构设计的一个关键挑战是 NoC 设计人员可以使用过多的性能增强、节能和容错技术，以及必须驾驭的巨大设计空间，以同时降低功耗、提高可靠性、提高性能和维持 QoS。这项研究提出了一种新的跨层、跨领域方法，涵盖电路、架构、机器学习算法和应用，旨在设计节能、可靠和可扩展的片上网络。这项研究将产生 (1) 新颖的跨层设计技术，该技术采用整体方法，同时降低功耗，同时仍实现片上网络的可靠性和性能目标，(2) 对使用适合硬件的 ML 的基本理解NoC 设计优化，(3) 用于在网络执行期间监控和收集关键数据和关键设计参数以优化 NoC 设计的软件和硬件技术，以及 (4) 建模和仿真工具，将改进架构社区用于评估可扩展性的设计方法NoC。拟议的研究弥合了在电路和架构级别设计电源管理和容错技术的硬件架构师与开发预测和优化技术的机器学习科学家之间的一个非常重要的差距。由于其跨领域性质，拟议的研究有可能显着改变下一代 CMP 和片上系统 (SoC) 的设计，因为必须做出影响功耗、性能和可靠性的复杂决策。该研究还将发现与教学和培训相结合，在教育中发挥重要作用。 PI 致力于并将继续扩大外展活动，作为拟议项目的一部分，做出必要的努力来吸引和培训该领域的少数族裔学生。

项目成果

期刊论文数量（17）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks

GCNAX：灵活且节能的图卷积神经网络加速器

DOI：
10.1109/hpca51647.2021.00070
发表时间：
2021-02
期刊：
2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA
影响因子：
0
作者：
Li, Jiajun;Louri, Ahmed;Karanth, Avinash;Bunescu, Razvan
通讯作者：
Bunescu, Razvan

SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference

SPACX：用于 DNN 推理的基于硅光子学的可扩展 Chiplet 加速器

DOI：
10.1109/hpca53966.2022.00066
发表时间：
2022-04-01
期刊：
2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
影响因子：
0
作者：
Yuan Li;A. Louri;Avinash Karanth
通讯作者：
Avinash Karanth

TSA-NoC: Learning-Based T hreat Detection and Mitigation for S ecure Network-on-Chip A rchitecture

TSA-NoC：用于安全片上网络架构的基于学习的威胁检测和缓解

DOI：
10.1109/mm.2020.3003576
发表时间：
2020-09
期刊：
IEEE Micro
影响因子：
3.6
作者：
Wang, Ke;Zheng, Hao;Louri, Ahmed
通讯作者：
Louri, Ahmed

CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning

CURE：使用强化学习的高性能、低功耗、可靠的片上网络设计

DOI：
10.1109/tpds.2020.2986297
发表时间：
2020-04
期刊：
IEEE Transactions on Parallel and Distributed Systems
影响因子：
5.3
作者：
Wang, Ke;Louri, Ahmed
通讯作者：
Louri, Ahmed

Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures

Adapt-NoC：适用于异构众核架构的灵活片上网络设计

DOI：
10.1109/hpca51647.2021.00066
发表时间：
2021-02-01
期刊：
2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
影响因子：
0
作者：
Hao Zheng;Ke Wang;A. Louri
通讯作者：
A. Louri