SBIR Phase I: High Fidelity EUV PhotoMasks

SBIR 第一阶段：高保真 EUV 光掩模

• 批准号: 1747341
• 负责人: Supriya Jaiswal
• 金额: $ 22.5万
• 依托单位: Astrileux Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2018
• 资助国家: 美国
• 起止时间: 2018-01-01 至 2019-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1747341&HistoricalAwards=false
• 关键词: SBIR; Phase; Fidelity; EUV; PhotoMasks

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to drive the next generation of advanced computing power and performance, by manufacturing integrated circuits, the fundamental units of electronic systems, at length scales of 7 nm and smaller. Today?s central processing units (CPUs) each contain 7.2 Bn chips and over 1.2 sextillion chips are manufactured per year to meet computing demands. Next generation technology is expected to enable artificial intelligence and machine learning through both conventional computing and potentially neuromorphic paradigms, bringing to reality transformative applications such as self-driving cars and smart buildings. As Moore?s law continues to set the pace of technological advancement, chipmakers will deploy new EUV (Extreme Ultraviolet) lithography tools, using light of 13.5 nm to pattern integrated circuits or chip architecture into silicon wafers, for the next three generations of technology. Chipmakers strive to bring about the readiness of EUV technology in 2019. The global demand for next generation electronics is forever increasing as the population grows above 7 Bn. However, the global supply of electronics constantly faces challenges to reduce costs and deliver technology beyond Moore?s Law.The proposed project addresses the challenges related to high volume manufacturing at the 7 nm node for lithography tools and its components. For example, an EUV photomask, a high commodity component, patterns and replicates integrated circuit design into silicon wafers. Current EUV photomasks have a sub-optimal manufacturing yield of ~60% and suffer from defectivity which arises during fabrication of its architecture. During operational use the photomask sustains damage from the debris generated by the EUV plasma light source that implants in the mask and inevitably replicates in the wafer, destroying the integrated chip pattern. In high volume manufacturing, these issues manifest in the wafer yield, the reusability of a mask, and drive the need for high cost real-time inspection and metrology. A new EUV photomask which promises greater robustness to defects, a higher manufacturing yield, more reusability of masks in operations and a longer lifetime is presented. The goals of the project are to evaluate new integrated architecture for the EUV mask design, develop a higher yield fabrication process and characterize the EUV performance. More robust photomasks reduce the capital outlay required for in-situ metrology and inspection and ultimately bring down the cost of next generation electronics.

这项小型企业创新研究（SBIR）I阶段项目的更广泛的影响/商业潜力是通过制造综合电路，电子系统的基本单元，7 nm和较小的尺度来推动下一代高级计算能力和性能。如今，中央加工单元（CPU）每个都包含7.2亿芯片，每年制造超过1.2亿芯片以满足计算需求。预计下一代技术将通过常规计算和潜在的神经形态范式来实现人工智能和机器学习，从而为现实的变革性应用（例如自动驾驶汽车和智能建筑物）带来。随着摩尔的法律继续设定技术进步的步伐，芯片制造商将使用13.5 nm的光线来部署新的EUV（极端紫外线）光刻工具，以将集成的电路或芯片建筑模式化到硅Wafers中，以实现接下来的三代技术。 Chipmakers努力在2019年实现EUV技术的准备。随着人口的增长超过70亿，全球对下一代电子产品的需求永远在增加。但是，全球电子设备的供应不断面临降低成本并将技术提供在摩尔定律之外的挑战。拟议的项目解决了与7 nm节点在光刻工具及其组件的7 nm节点上相关的挑战。例如，EUV光掩膜，高商品组件，模式并将集成的电路设计复制到硅晶片中。当前的EUV光掩膜的次优制造产量约为60％，并且在其建筑制造过程中产生的缺陷。在操作使用过程中，光掩膜会遭受EUV等离子光源产生的碎屑，该碎屑植入面罩中并不可避免地将其复制到晶圆中，从而破坏了综合的芯片模式。在大量制造中，这些问题在晶圆产量，面罩的可重复性中表现出来，并推动了高成本实时检查和计量的需求。提出了一种新的EUV照片，它有望具有更大的鲁棒性，更高的制造产量，掩模在操作中的更多可重复使用性和更长的寿命。该项目的目标是评估EUV面膜设计的新综合体系结构，开发更高的产量制造过程并表征EUV性能。更健壮的光掩膜减少了原位计量和检查所需的资本支出，并最终降低了下一代电子产品的成本。