SBIR Phase II: Next Generation High Performance EUV Photomasks.

SBIR 第二阶段：下一代高性能 EUV 光掩模。

• 批准号: 1927546
• 负责人: Supriya Jaiswal
• 金额: $ 75万
• 依托单位: Astrileux Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-10-01 至 2023-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1927546&HistoricalAwards=false
• 关键词: SBIR; Phase; II; Next; Generation

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to drive the next generation of advanced computing power and performance by manufacturing integrated circuits (ICs) at 7 nm and smaller. Today's central processing units (CPUs) contain 7.2 B chips and over 1.2 sextillion chips are manufactured per year. Next generation technology is expected to enable artificial intelligence and machine learning through both conventional computing and potentially new paradigms for transformative applications such as self-driving cars and smart buildings, but new ways are needed to make appropriate chips. The proposed project will develop a technology to address this need as chipmakers meet their desired goals. The proposed project addresses challenges related to high volume manufacturing at the 7 nm node for lithography tools and their components. An EUV photomask, a high commodity component, patterns and replicates integrated circuit design into silicon wafers. Current EUV photomasks have a sub-optimal manufacturing yield of ~65% and suffer from defectivity during fabrication of its architecture. During operational use the photomask sustains damage from the debris generated by the EUV plasma light source that implants in the mask and inevitably replicates in the wafer, destroying the integrated chip pattern. In high volume manufacturing, these issues manifest in the wafer yield, the reusability of a mask, and drive the need for high cost real-time inspection and metrology. We propose a new EUV photomask which promises a higher robustness to defects, a higher manufacturing yield, better uniformity and more reusability of masks in operations and longer lifetime. The goals of the project are to evaluate new integrated architecture for the EUV mask design, develop a higher yield fabrication process and characterize their EUV performance. More robust architectures reduce capital outlay requirements for in-situ metrology and inspection and ultimately bring down the cost of next generation electronics.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

这项小型企业创新研究（SBIR）II期项目的更广泛的影响/商业潜力是通过制造7 nm及更小的制造综合电路（ICS）来推动下一代高级计算能力和性能。当今的中央加工单元（CPU）包含7.2 B芯片，每年制造超过1.2亿芯片。预计下一代技术将通过常规计算和可能的新型范式（例如自动驾驶汽车和智能建筑物）来实现人工智能和机器学习，但是需要新的方法来制作适当的芯片。 拟议的项目将开发一项技术来满足这种需求，因为芯片制造商满足了他们所需的目标。拟议的项目解决了与7 nm节点在光刻工具及其组件的7 nm节点上相关的挑战。 EUV光掩膜，高商品组件，模式并将集成的电路设计复制到硅晶片中。当前的EUV光罩的次优制造产量约为65％，并且在其建筑制造过程中遭受了缺陷。在操作使用过程中，光掩膜会遭受EUV等离子光源产生的碎屑，该碎屑植入面罩中并不可避免地将其复制到晶圆中，从而破坏了综合的芯片模式。在大量制造中，这些问题在晶圆产量，面罩的可重复性中表现出来，并推动了高成本实时检查和计量的需求。我们提出了一项新的EUV光掩膜，该照片有望具有更高的鲁棒性，更高的制造产量，更好的均匀性以及在操作中蒙版的重复使用和更长的寿命。该项目的目标是评估EUV面膜设计的新综合体系结构，开发更高的产量制造过程并表征其EUV性能。更健壮的体系结构减少了对原位计量和检查的资本支出要求，并最终降低了下一代电子产品的成本。该奖项反映了NSF的法定任务，并被认为是值得通过基金会的知识分子优点和更广泛影响的评估来评估值得支持的。