XPS: FULL: CCA: Collaborative Research: SPARTA: a Stream-based Processor And Run-Time Architecture

XPS：完整：CCA：协作研究：SPARTA：基于流的处理器和运行时架构

• 批准号: 1547036
• 负责人: Ahmed Louri
• 金额: $ 30.73万
• 依托单位: George Washington University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-05-15 至 2020-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1547036&HistoricalAwards=false
• 关键词: XPS; FULL; CCA; Collaborative; Research

Computer systems have undergone a fundamental transformation recently, from single‐core processors to devices with increasingly higher core counts within a single chip. The semi‐conductor industry now faces the infamous power and utilization walls, that is, physical constraints such as levels of power and energy consumption, but also reliability of the various components, must be taken into account not only during the chip fabrication process, but also when generating machine code and during program execution. To meet these challenges, heterogeneity in design, both at the architecture and technology levels, will be the prevailing approach for energy efficient computing as specialized cores, accelerators, and graphical processing units (GPUs) can eliminate the energy overheads of general‐purpose homogeneous cores. However, with future technological challenges pointing in the direction of on‐chip heterogeneity, and because of the traditional difficulty of parallel programming, it becomes imperative to produce new system software stacks that can take advantage of the heterogeneous hardware. This project proposes to rethink the whole hardware‐software interface, by researching novel ways to design many‐core chip architectures and weaving heterogeneous components together and binding them by a fast and energy efficient on‐chip interconnection network. On top of it will lay a system software layer to efficiently drive applications and map them onto the best suited components of the chip. Both the hardware and software layer are encompassed by a novel execution model, which describes how to orchestrate the various parts of a program in the most efficient way (be it with respect to power and energy, performance, or reliability). To achieve these goals, the development of a new model of computation called SPARTA (Stream-based Processor And RunTime Architecture) is proposed. The proposed model combines a new runtime and compiler technology with a hierarchical heterogeneous many‐core chip and features hardware mechanisms for stream‐based fine‐grain program execution models to be reflected in different new software/hardware systems. Many issues are be envisioned, including programmability, scalability, performance evaluation, and power efficiency. Specifically, the goal is to identify the major challenges and obstacles toward an efficient exploitation of parallelism and scalability. To do so, traditional approaches will be re-evaluated by studying a collection of representative programs. A vertical design methodology is then proposed to effectively address the above challenges through the SPARTA approach and its implementation. In particular, the proposed cross-layer methodology consists of (a) a programming/execution model that will combine the Codelet model (leveraging our past research in dataflow models and extensions) with generalized streams: the Streaming Codelets, (b) an architecture model that will efficiently support the Streaming Codelets in heterogeneous hardware, and (c) a system software Stack that will be capable of effectively mapping Streaming Codelets to the proposed architecture. Finally, a qualitative and quantitative study of SPARTA will be performed via selected benchmarks and a consolidated methodology based on experimentation and analysis. The holistic cross-layer design methodology spanning the hardware/software stack and the reliability techniques developed from this research will significantly impact next generation multi‐core and System‐on‐Chip (SoC) architectures with improvements in energy efficiency, programmability, performance and robustness.

从单个核心处理器到单个芯片中核心计数越来越高的设备，计算机系统最近进行了基本转换。现在，指挥行业面临着臭名昭著的功率和利用墙，即，不仅必须在芯片制造过程中，而且在生成机器代码和程序执行过程中，不仅要考虑到各种组件的物理约束，而且还必须考虑到各种组件的可靠性。为了应对这些挑战，在建筑和技术水平上，设计的异质性将成为能源有效计算的现行方法，作为专门的核心，加速器和图形处理单元（GPU），可以消除一般同质核的一般能量架设。但是，随着未来的技术挑战指出了芯片异质性的方向，并且由于并行编程的传统困难，必须生产新的系统软件堆栈以利用异质性硬件的优势。该项目提议通过研究设计许多核心芯片架构的新方法来重新考虑整个硬件＆＃8208;软件界面，并将其编织异质组件融合在一起，并通过快速而节能的芯片互连网络来绑定它们。最重要的是，将放置系统软件层，以有效地驱动应用程序并将其映射到芯片的最佳组件上。硬件和软件层都包含一个新颖的执行模型，该模型描述了如何以最有效的方式来协调程序的各个部分（无论是在功率和能源，性能，性能或可靠性方面）。为了实现这些目标，提出了一种新的计算模型，称为Sparta（基于流的处理器和运行时体系结构）。提出的模型将新的运行时和编译器技术与层次异质的许多核心芯片结合在一起，并具有基于流的Fine＆＃8208; Grain＆＃8208; grain程序执行模型的硬件机制，以反映在不同的新软件/硬件系统中。设想许多问题，包括可编程性，可伸缩性，绩效评估和功率效率。具体而言，目标是确定有效利用并行性和可扩展性的主要挑战和障碍。为此，通过研究一系列代表性计划，将重新评估传统方法。然后提出了一种垂直设计方法，以通过Sparta方法及其实施有效地解决上述挑战。特别是，提出的跨层方法包括（a）一个编程/执行模型，该模型将结合Codelet模型（利用我们过去在数据流模型和扩展中的研究研究）与广义流：（b）一个体系结构模型，该模型将有效地支持Codeles的架构模型，该模型将有效地启动codeles，并将启动的软件启动，并（C）启动，并（Codeled）启用了系统的启动，并将（C）施加了（c），并将其启用，并将（C）施加了（C）。 建筑学。最后，将通过选定的基准和基于实验和分析的合并方法进行定性和定量研究。整体跨层设计方法涵盖了硬件/软件堆栈以及这项研究开发的可靠性技术，将显着影响下一代Multi＆＃8208; core and System＆＃8208; on Chip（SOC）架构，并提高了能源效率，可编程性，性能，绩效和鲁棒性。