Collaborative Research: CSR: Small: Cross-layer learning-based Energy-Efficient and Resilient NoC design for Multicore Systems

协作研究：CSR：小型：基于跨层学习的多核系统节能和弹性 NoC 设计

• 批准号: 2321224
• 负责人: Ahmed Louri
• 金额: $ 37.5万
• 依托单位: George Washington University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2321224&HistoricalAwards=false
• 关键词: Collaborative; Research; CSR; Small; Cross; Collaborative; Research; CSR; Small; Cross

The proliferation of multiple cores on the chip has signaled the advent of communication-centric, rather than computation-centric systems. Consequently, the design of low latency, high bandwidth, power-efficient, and reliable Network-on-Chips (NoCs) is proving to be one of the most critical challenges to achieving the performance potential of future multicore systems. However, as multicores are facilitating an enormous integration capacity, rapid transistor scaling has led to a steady degradation of the device and circuit reliability: unpredictable device behavior will undeniably increase and will result in a significant increase in faults (both permanent and transient), and hardware failures. The ramifications for the NoC are immense: a single fault in the NoC may paralyze the working of the entire chip. While considerable efforts are undertaken to tackle the reliability challenge of NoCs, most current solutions concentrate on local optimizations within the entire NoC abstractions (e.g., circuit, message, and network layers). These solutions tend to possess limited knowledge of the overall system and are therefore reactive in behavior, making worst-case assumptions and overprovisioning, and as a result, they introduce significant power, area, and performance overheads while not completely solving the reliability challenge.This research project tackles the critical NoC reliability challenge by developing a comprehensive, cooperative, and adaptive multi-layer approach for designing reliable NoCs from fault-susceptible components, with globally-optimized power, performance, and costs. To achieve this research goal, this project is organized into four interrelated research tasks. First, this research project conducts a comprehensive study of the fundamental mechanisms that underlie the reliability issues across NoC abstractions. A detailed analysis of the dynamic interactions of NoC abstractions and design trade-offs. Second, the research project develops a cross-layer NoC architecture for resilient on-chip communication with machine-learning-based optimization. Third, this research project aims to incorporate the application layer and off-chip communications and develops a holistic design framework that can automatically capture and adapt to the various computation and communication requirements of different applications with optimized performance, power, and reliability. Finally, the project evaluates the designed framework by developing a cycle-accurate simulation framework and an FPGA prototype. This project will significantly advance the fundamental understanding of the interplay between the NoC and the rest of the components on the chip (cores, memory, etc.) as well as design tradeoffs between performance, power, reliability, and cost in future massively defective nanometer technologies. The developed NoC framework will benefit future multi-core architectures and computing systems with system-level performance and reliability improvements.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

芯片上多个核心的扩散表明以通信为中心而不是以计算为中心的系统的出现。因此，低潜伏期，较高的带宽，效力和可靠的网络（NOC）的设计被证明是实现未来多核心系统的性能潜力的最关键挑战之一。但是，随着多学院正在促进巨大的集成能力，快速晶体管缩放导致设备的稳定下降和电路可靠性：不可预测的设备行为将不可否认地增加，并且会导致故障（永久和瞬态）和硬件故障的故障显着增加。 NOC的后果是巨大的：NOC中的单个故障可能会使整个芯片的工作瘫痪。尽管为应对NOC的可靠性挑战而竭尽全力，但当前大多数解决方案都集中在整个NOC抽象（例如电路，消息和网络层）中的本地优化。这些解决方案倾向于对整个系统具有有限的知识，因此在行为上具有反应性，使最坏的假设和过度覆盖能力，因此，它们引入了重要的能力，区域和性能间接费用，而不是完全解决可靠性挑战。本研究项目通过与全面的合作和适应性的构建方法来应对重要的NOC可靠性挑战，以实现合作和适应性的构图，并确定了适度的构图，该方法是在适当的挑战中，该研究项目的设计项目是合作，适度的，该方法的设计项目，并确定了适应性的构图。全球优化的功率，性能和成本。为了实现这一研究目标，该项目被组织成四个相互关联的研究任务。首先，该研究项目对基本机制进行了全面研究，这些基本机制是NOC抽象跨越可靠性问题的基础。对NOC抽象和设计权衡的动态相互作用的详细分析。其次，研究项目开发了一种跨层NOC体系结构，用于具有基于机器学习的优化的弹性芯片通信。第三，该研究项目旨在结合应用层和芯片外通信，并开发一个整体设计框架，可以自动捕获并适应具有优化性能，功率和可靠性的不同应用程序的各种计算和通信要求。最后，该项目通过开发循环精确的仿真框架和FPGA原型来评估设计的框架。该项目将大大提高对NOC与芯片（内核，内存等）中其余组件之间相互作用的基本理解，以及在未来的大量缺陷纳米技术中的性能，功率，能力，可靠性和成本之间的设计权衡。开发的NOC框架将使未来的多核架构和计算系统受益于系统级的性能和可靠性改进。该奖项反映了NSF的法定任务，并被认为是值得通过基金会的知识分子优点和更广泛影响的评估评估标准来通过评估来获得支持的。