SHF: Small: Collaborative Research: Power-Efficient and Reliable 3D Stacked Reconfigurable Photonic Network-on-Chips for Scalable Multicore Architectures

SHF：小型：协作研究：用于可扩展多核架构的高效且可靠的 3D 堆叠可重构光子片上网络

• 批准号: 1318981
• 负责人: Avinash Karanth
• 金额: $ 14.5万
• 依托单位: Ohio University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-08-01 至 2018-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1318981&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Power; SHF; Small; Collaborative; Research; Power

As power dissipation on a single-chip is increasing at an alarming rate due to massive integration of digital circuits, multicore design has become the only technique to scale performance. Multicores with tens to hundreds of cores are already available in the marketplace and future projections call for thousands of cores on the chip. To achieve scalable computing performance from the multicores, the communication between cores should also scale in bandwidth while significantly reducing the power consumption. Scaling the performance of the on-chip communication fabric, called the Network-on-Chip (NoC), has proven to be a significant challenge with traditional metallic interconnects due to fundamental signaling issues such as power dissipation, electromagnetic interference, crosstalk and reflections. Several studies and roadmaps have indicated that disruptive technology solutions such as photonics have the potential to alleviate the critical bandwidth, power and latency challenges of future multicores. This research seeks to exploit the unique advantages of photonic interconnects and 3D stacking technologies to develop scalable, energy-efficient, bandwidth-reconfigurable and reliable NoCs for future multicores. There are three goals of the proposed research: first, it will investigate and develop 3D stacked photonic NoC architectures and topologies that maximize performance and improve energy-efficiency; second, it will develop runtime reconfiguration techniques that can adapt the network to the communication needs of the application, thereby improving performance on a per-application basis; and third, it will result in an extensive modeling and simulation framework to be used for designing and validating future photonic NoC architectures.This research has far reaching broader impacts. This research is uniquely positioned to leverage two emerging technologies namely photonics and 3D stacking to meet the multicore challenge and will significantly benefit society. The proposed research is essential to continue the growth of computing performance that our society depends upon, and will result in digital devices ranging from smartphones to laptops with faster response time and improved reliability. By investigating the design of energy-efficient and high-bandwidth photonic-3D NoC architectures, this proposal describes a transformative and viable approach to combine technology, algorithm and applications' research to enable building scalable multicores. The cross-cutting nature of this research will foster new research directions in several areas, spanning technology/energy-aware NoC design, novel computer architectures, and cutting-edge modeling and simulations tools for emerging technologies. This research will also play a major role in education by integrating discovery with teaching and training. Several graduate students will be directly involved with all phases of the project from which the core parts of their dissertations and theses will be derived. It will also benefit a wider audience of graduate and undergraduate students by incorporating the new research into several courses on computer architecture and parallel processing taught by the PIs. Finally, the results and findings of the proposed research will be disseminated to researchers, engineers and educators through technical publications and presentations.

由于数字电路的大规模整合，单芯片上的功率耗散以惊人的速度增加，因此多核设计已成为扩展性能的唯一技术。市场上已经有数十个至数百枚核心的多门，未来的预测要求数千个芯片上有数千个核心。为了实现Multicores的可扩展计算性能，核心之间的通信也应在带宽方面扩展，同时大大降低功耗。由于基本的信号问题，例如功率耗散，电磁干扰，串扰和反射，因此，在传统的金属互连方面扩展了称为网络芯片（NOC）（NOC）的片上的性能，这是一个重大挑战。几项研究和路线图表明，诸如光子学之类的破坏性技术解决方案有可能减轻未来多学院的关键带宽，功率和潜伏期挑战。这项研究旨在利用光子互连和3D堆叠技术的独特优势，以开发可扩展，能效，带宽 - 可靠性和可靠的NOC，以用于将来的多学院。拟议的研究有三个目标：首先，它将调查和开发3D堆叠的光子NOC架构和拓扑结构和拓扑，以最大程度地提高性能并提高能源效率；其次，它将开发运行时重新配置技术，可以使网络适应应用程序的通信需求，从而以每次应用程序提高性能；第三，这将导致广泛的建模和仿真框架，用于设计和验证未来的光子NOC体系结构。这项研究具有更大的影响。这项研究的独特位置可以利用两种新兴技术，即光子学和3D堆叠来应对多项挑战，并将极大地使社会受益。拟议的研究对于继续我们社会所依赖的计算性能的增长至关重要，并将导致数字设备从智能手机到具有更快响应时间和可靠性提高的笔记本电脑的数字设备。通过研究节能和高带宽光子3D NOC体系结构的设计，该提案描述了一种结合技术，算法和应用研究的变革性可行的方法，以启用建筑可扩展的多学院。这项研究的横切性质将在几个领域促进新的研究方向，涵盖技术/能源感知的NOC设计，新颖的计算机架构以及新兴技术的尖端建模和模拟工具。这项研究还将通过将发现与教学和培训相结合，在教育中发挥重要作用。几位研究生将直接参与该项目的所有阶段，其论文和论文的核心部分将得出。通过将新的研究纳入有关计算机架构和PIS教授的平行处理的几门课程中，这也将使更多的研究生和本科生受益。最后，拟议研究的结果和发现将通过技术出版物和演示文稿传播给研究人员，工程师和教育者。