SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures for Optimized Energy, Performance and Reliability

SHF：中：协作研究：支持机器学习的片上网络架构，可优化能源、性能和可靠性

• 批准号: 1703013
• 负责人: Avinash Karanth
• 金额: $ 50万
• 依托单位: Ohio University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-06-01 至 2023-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1703013&HistoricalAwards=false
• 关键词: SHF; Medium; Collaborative; Research; Machine

Network-on-Chip (NoC) architectures have emerged as the prevailing on-chip communication fabric for multicores and Chip Multiprocessors (CMPs). However, as NoC architectures are scaled, they face serious challenges. A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing, energy efficient and fault tolerant techniques available to NoC designers and the large design space that must be navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. This research proposes a new cross-layer, cross-cutting methodology spanning circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient, reliable and scalable NoCs. This research will result in (1) novel cross-layer design techniques that take a holistic approach of simultaneously reducing power consumption, while still achieving reliability and performance goals for NoCs, (2) a fundamental understanding of the use of hardware-amenable ML for NoC design optimization, (3) software and hardware techniques for monitoring and collecting critical data and key design parameters during network execution to optimize NoC design, and (4) modeling and simulation tools that will improve the architecture community's design methodologies for evaluating scalable NoCs. The proposed research bridges a very important gap between hardware architects who design power management and fault tolerant techniques at the circuit and architecture level and machine learning scientists who develop predictive and optimization techniques. Due to its cross-cutting nature, the proposed research has the potential to significantly transform the design of next-generation CMPs and System-on-Chips (SoCs) where complex decisions have to be made that affect the power, performance and reliability. The research will also play a major role in education by integrating discovery with teaching and training. The PIs are committed and will continue to expand on outreach activities as part of the proposed project by making the necessary efforts to attract and train minority students in this field.

片上网络（NOC）架构已成为用于多学院和芯片多处理器（CMP）的流行片上通信结构。但是，随着NOC架构的扩展，它们面临严重的挑战。当今解决优化的NOC体系结构设计的一个关键挑战是，可供NOC设计师使用的大量增强性能，节能和容忍度的技术以及必须导航的大型设计空间，以同时降低功率，提高可靠性，提高性能，提高性能并保持QoS。这项研究提出了一种跨越电路，体系结构，机器学习算法和应用的新的跨层，横切方法，旨在设计能效，可靠和可扩展的NOC。这项研究将导致（1）新颖的跨层设计技术，这些技术采用同时减少功耗的整体方法，同时仍然实现NOC的可靠性和性能目标，（2）对使用硬件无关的ML用于NOC设计的使用的基本了解，（3）在进行NOC设计，（3）在监视和收集键入的网络设计范围（3）启用了4个型模型（4）以及将改善架构社区设计方法的仿真工具，用于评估可扩展的NOC。拟议的研究弥合了在巡回赛和建筑级别设计电源管理和容忍技术的硬件建筑师之间的一个非常重要的差距，以及开发预测性和优化技术的机器学习科学家。由于其横切性质，拟议的研究有可能显着改变下一代CMP和芯片系统（SOC）的设计，在这些设计中必须做出复杂的决定，以影响力量，性能和可靠性。这项研究还将通过将发现与教学和培训相结合，在教育中发挥重要作用。 PIS是努力的，并将通过在该领域吸引和培训少数族裔学生的必要努力来继续扩大外展活动，作为拟议项目的一部分。

项目成果

Parallel Dot Products Using Silicon Photonics

使用硅光子学的并行点积

• DOI: 10.1109/ipc48725.2021.9592936
• 发表时间: 2021
• 期刊: 2021 IEEE Photonics Conference (IPC
• 作者: Wolff, Andy;Shiflett, Kyle;Karanth, Avinash
• 通讯作者: Karanth, Avinash

Bitwise Neural Network Acceleration Using Silicon Photonics

• DOI: 10.1145/3453688.3461515
• 发表时间: 2021-06
• 期刊: Proceedings of the 2021 Great Lakes Symposium on VLSI
• 作者: Kyle Shiflett;Avinash Karanth;A. Louri;Razvan C. Bunescu

A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration

• DOI: 10.1109/tpds.2023.3327535
• 发表时间: 2024-01
• 期刊: IEEE Transactions on Parallel and Distributed Systems
• 影响因子: 5.3
• 作者: Yuan Li;A. Louri;Avinash Karanth

Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques

• DOI: 10.1109/tc.2018.2875476
• 发表时间: 2019-03-01
• 期刊: IEEE TRANSACTIONS ON COMPUTERS
• 影响因子: 3.7
• 作者: Fettes, Quintin;Clark, Mark;Louri, Ahmed
• 通讯作者: Louri, Ahmed

Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning

通过强化学习进行硬件级线程迁移以减少片上数据移动

• DOI: 10.1109/tcad.2020.3012650
• 发表时间: 2020
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: Fettes, Quintin;Karanth, Avinash;Bunescu, Razvan;Louri, Ahmed;Shiflett, Kyle
• 通讯作者: Shiflett, Kyle