Collaborative Research: SHF: Medium: Tiny Chiplets for Big AI: A Reconfigurable-On-Package System

合作研究：SHF：中：用于大人工智能的微型芯片：可重新配置的封装系统

• 批准号: 2403408
• 负责人: Yu Cao
• 金额: $ 80万
• 依托单位: University of Minnesota-Twin Cities
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2024
• 资助国家: 美国
• 起止时间: 2024-07-01 至 2028-06-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2403408&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Medium; Tiny

As monolithic chips reach their technological and practical limits, the integration of chiplets is emerging as the primary mechanism to continuously scale up processor performance, improve power efficiency, enhance IP reuse at low cost, and expedite time-to-market. This new concept of composable chiplets is particularly appealing to the artificial intelligence (AI) sector, which is in a pressing need to deliver computing chips to support increasingly complex and diverse cognitive algorithms. This project aims to pioneer such a computing system, including new architectural and design automation tools, for massive AI workloads. The envisioned system will benefit various scenarios, ranging from high-performance computing applications to mobile and edge devices. This project also addresses the skill shortage in the semiconductor area, a crucial aspect for reshoring the semiconductor industry. It involves training students in the areas of heterogeneous system design, AI architectures, and design automation. The investigators plan to improve the knowledge base through new curriculum development, engaging undergraduate students in research through Research Experiences for Undergraduates (REU) supplement, and participating in outreach programs customized for K-12 students. In addition, this project will advocate web-based knowledge dissemination including releasing software codes and novel designs. Several workshops and tutorials promoting chiplet-based co-design have been organized by the investigators and will be continued.Distinguished from current practice of 2.5D/3D heterogeneous integration (HI), this project aims to transform the architecture of chiplet-based design through three unique perspectives: Miniaturization to reduce the chiplet size to the minimum (tiny chiplets) for high composability, guided by AI computing cores; Very-large-scale integration to integrate thousands of tiny chiplets to scale up computing power and diversity for big AI applications, offering unprecedented flexibility and efficiency for AI algorithm and system designers; and Reconfiguration on the package to enable adaptation to varying workloads and address thermal and reliability concerns in 2.5D/3D packaging. These innovations will push the limits of architecture and physical design, addressing challenges related to chiplet definition, interconnection, power and thermal integrity, and workload mapping. The objective is to create a suite of design automation tools, streamlining the complete design process of reconfigurable chiplet-based systems for big AI computing.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

随着单片芯片达到其技术和实际限制，芯片的整合正在成为不断扩大处理器性能，提高功率效率，以低成本以及快速推销市场的IP再利用的主要机制。这种合并chiplets的新概念特别有吸引力，对人工智能（AI）部门尤其有吸引力，该部门迫切需要提供计算芯片，以支持日益复杂和多样化的认知算法。该项目旨在开拓这种计算系统，包括新的建筑和设计自动化工具，用于大规模的AI工作负载。设想的系统将使各种方案受益，从高性能计算应用程序到移动设备和边缘设备。该项目还解决了半导体区域的技能短缺，这是重新培养半导体行业的关键方面。它涉及在异质系统设计，AI架构和设计自动化领域的培训学生。调查人员计划通过新的课程开发来改善知识库，通过针对本科生（REU）补充的研究经验来吸引本科生研究，并参加为K-12学生定制的外展计划。此外，该项目将主张基于Web的知识传播，包括发布软件代码和新颖设计。研究人员已经组织了一些促进基于奇普的共同设计的研讨会和教程，并将继续进行。与当前的2.5D/3D/3D异质整合（HI）的实践不同，该项目旨在通过三个独特的观点来改变基于奇普的设计的构建：通过三个独特的观点：将奇普的尺寸降低到最小的芯片（薄薄的芯片）（薄薄的芯片）（薄薄的芯片），以占用薄薄的芯片（薄薄的芯片）。非常大规模的集成，以整合成千上万的微小芯片，以扩大大型AI应用程序的计算能力和多样性，为AI算法和系统设计师提供前所未有的灵活性和效率；并在包装上重新配置，以适应不同的工作负载，并以2.5D/3D包装解决热度和可靠性问题。这些创新将推动建筑和物理设计的限制，以应对与Chiplet定义，互连，功率和热完整性以及工作负载映射有关的挑战。目的是创建一套设计自动化工具，简化用于大型AI计算的基于可重新配置的基于Chiplet的系统的完整设计过程。该奖项反映了NSF的法定任务，并被认为值得通过基金会的知识分子优点和更广泛的影响评估标准通过评估来进行评估。