SHF: Small: Collaborative Research: Fast Sign-Off of Nanoscale Memory: From Predictive Device Modeling to Statistical Circuit Synthesis

SHF：小型：协作研究：纳米级存储器的快速签核：从预测设备建模到统计电路综合

• 批准号: 1016831
• 负责人: Yu Cao
• 金额: $ 22.49万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-08-15 至 2013-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1016831&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Fast

The scaling of on-chip memory is tremendously challenged by the excessive amount of process variations and reliability degradation at the 22nm node and below. In current practice, full custom design and extensive experimentation on test silicon are often necessary to achieve the desired performance under all process, voltage, and temperature conditions. Although such an expensive approach is acceptable in today?s chip design, it drastically reduces design productivity and predictability. The situation becomes even more severe when the ever-increasing nature of variations narrows the design window and exacerbates memory design complexity. This proposal aims to develop innovative methodologies that will enable fast sign-off of on-chip memory at the end of the silicon roadmap and beyond, through the seamless integration of predictive variability models, statistical sampling schemes, robust optimization algorithms, and efficient silicon characterization techniques. Furthermore, these new outcomes will be integrated into an online framework to statistically benchmark post-Si memory design, helping illustrate the diverse opportunities of memory design beyond the 10nm node. This research effort will facilitate fundamental research on reliable design with unreliable components, enhance design productivity for a wide range of applications, and expedite statistical design solution for emerging nanoelectronic devices. In addition, through novel education curricula and web-based dissemination tools, this project will transfer the newly developed design knowledge to a diverse population of students, who will lead the creation of future nanoscale integrated systems of all types, from computation, communication, to consumer electronics.

22 纳米及以下节点的工艺变化过多和可靠性下降，给片上存储器的扩展带来了巨大的挑战。在当前的实践中，通常需要对测试芯片进行全面的定制设计和广泛的实验，才能在所有工艺、电压和温度条件下实现所需的性能。尽管这种昂贵的方法在当今的芯片设计中是可以接受的，但它极大地降低了设计效率和可预测性。当不断增加的变化性质缩小了设计窗口并加剧了存储器设计的复杂性时，情况变得更加严重。该提案旨在开发创新方法，通过预测可变性模型、统计采样方案、稳健的优化算法和高效的芯片表征的无缝集成，在芯片路线图结束时及之后实现片上存储器的快速签核技术。此外，这些新成果将被集成到一个在线框架中，以对后硅内存设计进行统计基准测试，帮助说明 10 纳米节点之后内存设计的多样化机会。这项研究工作将促进对不可靠组件的可靠设计的基础研究，提高各种应用的设计生产力，并加快新兴纳米电子器件的统计设计解决方案。此外，通过新颖的教育课程和基于网络的传播工具，该项目将把新开发的设计知识传授给不同的学生群体，他们将领导创建未来所有类型的纳米级集成系统，从计算、通信到消费电子产品。