SHF: Small: Collaborative Research: Fast Sign-Off of Nanoscale Memory: From Predictive Device Modeling to Statistical Circuit Synthesis

SHF：小型：协作研究：纳米级存储器的快速签核：从预测设备建模到统计电路综合

• 批准号: 1016831
• 负责人: Yu Cao
• 金额: $ 22.49万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-08-15 至 2013-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1016831&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Fast

The scaling of on-chip memory is tremendously challenged by the excessive amount of process variations and reliability degradation at the 22nm node and below. In current practice, full custom design and extensive experimentation on test silicon are often necessary to achieve the desired performance under all process, voltage, and temperature conditions. Although such an expensive approach is acceptable in today?s chip design, it drastically reduces design productivity and predictability. The situation becomes even more severe when the ever-increasing nature of variations narrows the design window and exacerbates memory design complexity. This proposal aims to develop innovative methodologies that will enable fast sign-off of on-chip memory at the end of the silicon roadmap and beyond, through the seamless integration of predictive variability models, statistical sampling schemes, robust optimization algorithms, and efficient silicon characterization techniques. Furthermore, these new outcomes will be integrated into an online framework to statistically benchmark post-Si memory design, helping illustrate the diverse opportunities of memory design beyond the 10nm node. This research effort will facilitate fundamental research on reliable design with unreliable components, enhance design productivity for a wide range of applications, and expedite statistical design solution for emerging nanoelectronic devices. In addition, through novel education curricula and web-based dissemination tools, this project will transfer the newly developed design knowledge to a diverse population of students, who will lead the creation of future nanoscale integrated systems of all types, from computation, communication, to consumer electronics.

在22nm节点及以下的过程变化和可靠性降解中，片上内存的缩放率巨大的挑战。在目前的实践中，在所有过程，电压和温度条件下实现所需的性能通常是必要的，对测试硅的全面设计和广泛的实验通常是必需的。尽管在当今的芯片设计中可以接受这种昂贵的方法，但它大大降低了设计的生产力和可预测性。当变化的不断增长的性质缩小设计窗口并加剧了内存设计的复杂性时，情况就变得更加严重。该提案旨在开发创新的方法，这些方法将通过无缝整合预测可变性模型，统计抽样方案，可靠的优化算法和有效的硅特性技术，在硅路线图及其他地区进行快速签名。此外，这些新结果将集成到一个在线框架中，以统计基准SI内存设计，有助于说明10nm节点以外的内存设计机会。这项研究工作将促进对可靠设计的基本研究，并具有不可靠的组件，提高了广泛应用的设计生产力，并为新兴的纳米电子设备提供了加快的统计设计解决方案。此外，通过新颖的教育课程和基于Web的传播工具，该项目将将新开发的设计知识转移到各种各样的学生中，他们将领导未来的纳米级集成系统，从计算，通信到消费者电子产品。