SHF: Small: Collaborative Research: A Holistic Design Methodology for Fault-Tolerant and Robust Network-on-Chips (NoCs) Architectures
SHF:小型:协作研究:容错和鲁棒片上网络 (NoC) 架构的整体设计方法
基本信息
- 批准号:1420718
- 负责人:
- 金额:$ 20万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2014
- 资助国家:美国
- 起止时间:2014-07-15 至 2019-06-30
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Technology scaling down to the nanometer regime has aided the growth in transistors that have made multi-core architectures a power-efficient approach to harnessing parallelism and improving performance. Consequently, the design of low latency, high bandwidth, power-efficient and reliable Network-on-Chips (NoCs) is proving to be one of the most critical challenges to achieving the performance potential of future chips. While multicores are facilitating an enormous integration capacity, aggressive transistor scaling has also led to a steady degradation of the device and circuit reliability. Increased device wear-out (due to negative-bias temperature instability (NBTI), electro migration (EM) and hot carrier injection (HCI)) has exacerbated the waning reliability of transistors, thereby resulting in a significant increase in faults (both permanent and transient), and hardware failures. As faults manifest within the NoC substrate, multicore chips are faced with excessive delays and increased power consumption while recovering from the fault. While NoC reliability research has made significant strides at inter- and intra-router levels, there is still a lack of a holistic design approach covering the reliability of the entire NoC architecture, from device wear-out, to links and routers, to routing protocols, to applications in a cohesive manner.This project will develop a holistic design methodology that addresses the reliability of the entire NoC communication infrastructure (device, links, routers, routing algorithms, and topology) while minimizing energy footprint, reducing the area overhead and only marginally impacting performance. To achieve our goal of improving link fault-recovery, this project will develop techniques to maximize the utilization of the inter-router links with minimum power and area overhead. For the router, this project will propose intra-router reliability techniques with the goals of maximizing hardware utilization, reducing redundancy and area overhead, and minimizing router pipeline latency. Further, wear-leveling techniques developed by this project will improve the reliability of NoCs and the lifetime of the chip. Finally, the proposed techniques will be evaluated by developing fault models that are injected into the NoC and evaluate the fault coverage, performance degradation and energy efficiency through extensive modeling and simulation. The holistic design methodology spanning the entire NoC architecture and the reliability techniques developed from this project will positively impact the next generation multi-core and System-on-Chip (SoC) architectures with improvements in energy efficiency, performance and robustness to hard faults and soft errors. This project will play a major role in education by integrating discovery with teaching and training, and by attracting and training minority students in this field.
扩展到纳米制度的技术有助于使多核体系结构成为利用并行性和提高性能的力量方法的晶体管增长。因此,低潜伏期,较高的带宽,智力网络(NOC)的设计被证明是实现未来芯片的性能潜力的最关键挑战之一。虽然Multicores促进了巨大的集成能力,但侵略性晶体管缩放也导致了设备和电路可靠性的稳定下降。设备磨损增加(由于偏置温度不稳定(NBTI),电迁移(EM)和热载体注入(HCI))加剧了晶体管的衰落可靠性,从而导致故障(永久性和瞬态)和硬件故障的故障显着增加。由于故障在NOC底物中表现出来,多核芯片面临过多的延迟和增加的功耗,同时从故障中恢复过来。虽然NOC可靠性研究在相互和内部的层次级别取得了长足的进步,但仍然缺乏整体设计方法,涵盖了从设备磨损到链接,链接到路由协议到凝聚力的整个NOC体系结构的可靠性,并以凝聚力的方式来开发整体设计方法。算法和拓扑)同时最大程度地减少了能量足迹,减少了头顶的区域,并且只会影响略有影响的性能。为了实现我们改善链路故障恢复的目标,该项目将开发技术,以最大程度地利用与最小功率和面积开销的路由器间链接。对于路由器,该项目将提出途径内的可靠性技术,其目标是最大化硬件利用,减少冗余和面积开销,并最大程度地减少路由器管道延迟。此外,该项目开发的磨损水平技术将提高NOC的可靠性和芯片的寿命。最后,将通过开发被注入NOC的故障模型来评估所提出的技术,并通过广泛的建模和仿真评估故障覆盖,性能降解和能源效率。整个NOC架构的整体设计方法以及该项目开发的可靠性技术将对下一代多核和系统芯片(SOC)体系结构产生积极影响,并提高了能源效率,性能和鲁棒性对硬故障和软错误的稳健性。该项目将通过将发现与教学和培训结合在一起,并吸引和培训该领域的少数学生,从而在教育中发挥重要作用。
项目成果
期刊论文数量(0)
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Avinash Karanth其他文献
Ultracompact and Low-Power Logic Circuits via Workfunction Engineering
通过功函数工程实现超紧凑和低功耗逻辑电路
- DOI:
10.1109/jxcdc.2019.2962494 - 发表时间:
2019 - 期刊:
- 影响因子:2.4
- 作者:
T. F. Canan;S. Kaya;Avinash Karanth;A. Louri - 通讯作者:
A. Louri
Reconfigurable Gates with Sub-10nm Ambipolar SB-FinFETs for Logic Locking & Obfuscation
具有亚 10nm 双极 SB-FinFET 的可重构栅极,用于逻辑锁定
- DOI:
10.1109/mwscas48704.2020.9184509 - 发表时间:
2020 - 期刊:
- 影响因子:0
- 作者:
T. F. Canan;S. Kaya;H. Chenji;Avinash Karanth - 通讯作者:
Avinash Karanth
Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies
通过探索新兴技术的异构性实现片上网络的可持续性
- DOI:
10.1109/tsusc.2018.2861362 - 发表时间:
2019 - 期刊:
- 影响因子:3.9
- 作者:
Avinash Karanth;S. Kaya;A. Sikder;Daniel J. Carbaugh;S. Laha;D. DiTomaso;A. Louri;H. Xin;Junqiang Wu - 通讯作者:
Junqiang Wu
Reflections of Cybersecurity Workshop for K-12 Teachers
K-12 教师网络安全研讨会的思考
- DOI:
10.1145/3545945.3569761 - 发表时间:
2023 - 期刊:
- 影响因子:0
- 作者:
Chad Mourning;H. Chenji;Allyson Hallman;S. Kaya;Nasseef Abukamail;D. Juedes;Avinash Karanth - 通讯作者:
Avinash Karanth
SNAC: Mitigation of Snoop-Based Attacks with Multi-Tier Security in NoC Architectures
SNAC:通过 NoC 架构中的多层安全性缓解基于窥探的攻击
- DOI:
10.1145/3649476.3658769 - 发表时间:
2024 - 期刊:
- 影响因子:0
- 作者:
Siqin Liu;Saumya Chauhan;Avinash Karanth - 通讯作者:
Avinash Karanth
Avinash Karanth的其他文献
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{{ truncateString('Avinash Karanth', 18)}}的其他基金
Collaborative Research: DESC: Type II: Multi-Function Cross-Layer Electro-Optic Fabrics for Reliable and Sustainable Computing Systems
合作研究:DESC:II 型:用于可靠和可持续计算系统的多功能跨层电光织物
- 批准号:
2324645 - 财政年份:2023
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
Collaborative Research: SHF: Medium: EPIC: Exploiting Photonic Interconnects for Resilient Data Communication and Acceleration in Energy-Efficient Chiplet-based Architectures
合作研究:SHF:中:EPIC:利用光子互连实现基于节能 Chiplet 的架构中的弹性数据通信和加速
- 批准号:
2311544 - 财政年份:2023
- 资助金额:
$ 20万 - 项目类别:
Continuing Grant
SaTC: CORE: Small: Language Abstractions for Reconfigurable Hardware Monitors on Manycore Architectures
SaTC:CORE:Small:众核架构上可重新配置硬件监视器的语言抽象
- 批准号:
1936794 - 财政年份:2020
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
SHF: Medium: Collaborative Research: Photonic Neural Network Accelerator for Energy-efficient Heterogeneous Multicore Architectures
SHF:中:协作研究:用于节能异构多核架构的光子神经网络加速器
- 批准号:
1901192 - 财政年份:2019
- 资助金额:
$ 20万 - 项目类别:
Continuing Grant
SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures for Optimized Energy, Performance and Reliability
SHF:中:协作研究:支持机器学习的片上网络架构,可优化能源、性能和可靠性
- 批准号:
1703013 - 财政年份:2017
- 资助金额:
$ 20万 - 项目类别:
Continuing Grant
SHF: Medium: Collaborative Research: Scaling On-chip Networks to 1000-core Systems using Heterogeneous Emerging Interconnect Technologies
SHF:中:协作研究:使用异构新兴互连技术将片上网络扩展到 1000 核系统
- 批准号:
1513606 - 财政年份:2015
- 资助金额:
$ 20万 - 项目类别:
Continuing Grant
SHF: Small: Collaborative Research: Power-Efficient and Reliable 3D Stacked Reconfigurable Photonic Network-on-Chips for Scalable Multicore Architectures
SHF:小型:协作研究:用于可扩展多核架构的高效且可靠的 3D 堆叠可重构光子片上网络
- 批准号:
1318981 - 财政年份:2013
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
Collaborative Research:EAGER:Exploiting Heterogeneity in Emerging Interconnect Technologies for Building Highly Scalable and Power-Efficient Network-on-Chips for Many-core Systems
合作研究:EAGER:利用新兴互连技术的异构性为多核系统构建高度可扩展且高能效的片上网络
- 批准号:
1342657 - 财政年份:2013
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
Power-Efficient Reconfigurable Wireless Network-on-Chip (NoC) Interconnects for Future Many-core Architectures
适用于未来众核架构的高能效可重配置无线片上网络 (NoC) 互连
- 批准号:
1129010 - 财政年份:2011
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
CAREER: Design of Reconfigurable Power and Area-Efficient Nanophotonic Architectures for Future Multi-cores
职业:为未来多核设计可重构功率和面积高效的纳米光子架构
- 批准号:
1054339 - 财政年份:2011
- 资助金额:
$ 20万 - 项目类别:
Continuing Grant
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