SHF: Medium: Collaborative Research: Scaling On-chip Networks to 1000-core Systems using Heterogeneous Emerging Interconnect Technologies

SHF：中：协作研究：使用异构新兴互连技术将片上网络扩展到 1000 核系统

• 批准号: 1513606
• 负责人: Avinash Karanth
• 金额: $ 48万
• 依托单位: Ohio University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-08-01 至 2021-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1513606&HistoricalAwards=false
• 关键词: SHF; Medium; Collaborative; Research; Scaling

Power dissipation has become a fundamental barrier to scaling computing performance across all platforms from handheld, embedded systems, to laptops, to servers to data centers. Technology scaling down to the sub-nanometer regime has aided the growth in transistors per chip that has made multi-core architectures a power-efficient approach to harnessing parallelism and improving performance. The computing capabilities of these multi-core architectures can be unleashed only if the underlying Network-on-Chip (NoC) connecting the cores can provide the required bandwidth within the power budget of the chip. However, the design of power-efficient, low-latency and high-bandwidth NoCs using traditional metallic interconnects that can scale to 1000 cores and beyond, is proving to be a significant challenge of enormous proportions. Research has shown that emerging technologies such as photonics and wireless have the potential to alleviate the critical bandwidth, power, and latency challenges of future NoCs. However, hybrid NoC designs taking advantages of both photonics and wireless technologies have not been explored. This research proposes to lay the groundwork for completely re-thinking the NoC design and proposes to explore heterogeneity of emerging interconnect technology for designing performance scalable, and power-efficient NoCs. The overall objective is to combine multiple technologies to achieve our challenging goals of (1) scalability to 1000 cores, (2) power efficiency of at least a 50% power reduction as compared to the state-of-the-art metallic interconnects, and (3) high bandwidth and low latency across a wide variety of applications. First, at the architecture level, optics will be deployed for short-range ( 100 cores) to improve local communication and wireless for long-range communication in order to scale the number of cores to 1000 by providing sufficient global bandwidth. Second, at the circuit level, hybrid transceiver architectures will be explored to integrate novel ultra-low power wireless circuits based on SiGe/BiCMOS technology with optical waveguides and ring-resonators to provide the large bandwidth desired for kilo-core designs. Furthermore, wireless communication requirements will be addressed by designing mm-wave/THz frequency broadband and directional antennas based on advanced 3D printing technology. This proposal describes a transformative and viable approach combining technology, architecture, algorithms and applications research for designing scalable and energy-efficient NoCs. The cross-cutting nature of this research will foster new research directions in several areas, spanning technology/energy-aware NoC design, novel computer architectures, and cutting-edge modeling and simulations tools for emerging technologies.

功率耗散已成为从手持式，嵌入式系统到笔记本电脑到服务器到数据中心的所有平台扩展计算性能的基本障碍。扩展到子纳米级制度的技术有助于每个芯片的晶体管增长，这使多核体系结构成为利用并行性和提高性能的力量方法。仅当连接核心的基础网络（NOC）可以在芯片的功率预算内提供所需的带宽时，才能释放这些多核体系结构的计算功能。但是，使用传统的金属互连可以扩展到1000个核心及以后的传统金属互连的功率，低延迟和高带宽NOC的设计，这是对巨大比例的重大挑战。研究表明，诸如Photonics和Wireless之类的新兴技术有可能减轻未来NOC的关键带宽，功率和潜伏期挑战。但是，尚未探索具有光子学和无线技术优势的混合NOC设计。这项研究提出了为完全重新考虑NOC设计的基础，并提议探索新兴互连技术的异质性，以设计可扩展性能的性能和发电效率的NOC。总体目的是将多种技术结合起来，以实现（1）可伸缩到1000个内核的挑战性目标，（2）与最先进的金属互连相比，功率效率至少降低了50％，以及（3）在各种应用中，高带宽和低延迟。首先，在体系结构级别上，将部署光学功能（100个内核），以改善本地通信和无线通信，以通过提供足够的全球带宽来扩展核心数量到1000。其次，在电路级别上，将探索混合收发器架构，以基于SIGE/BICMOS技术与光学波导和环形谐振器相结合，以提供千核设计所需的大带宽。此外，将根据高级3D打印技术设计MM-WAVE/THZ频率宽带和定向天线来解决无线通信要求。该提案描述了一种结合技术，架构，算法和应用研究的变革性且可行的方法，用于设计可扩展和节能的NOC。这项研究的横切性质将在几个领域促进新的研究方向，涵盖技术/能源感知的NOC设计，新颖的计算机架构以及新兴技术的尖端建模和模拟工具。

项目成果

CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters

• DOI: 10.1109/hpca51647.2021.00058
• 发表时间: 2021-02
• 期刊: 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
• 作者: Jiajun Li;A. Louri;Avinash Karanth;Razvan C. Bunescu

GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks

• DOI: 10.1109/hpca51647.2021.00070
• 发表时间: 2021-02
• 期刊: 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
• 作者: Jiajun Li;A. Louri;Avinash Karanth;Razvan C. Bunescu

DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning

DozzNoC：利用机器学习通过低延迟稳压器减少 NoC 中的静态和动态能量

• DOI: 10.1109/ipdps47924.2020.00011
• 发表时间: 2020
• 期刊: 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS
• 作者: Clark, Mark;Chen, Yingping;Karanth, Avinash;Ma, Brian;Louri, Ahmed
• 通讯作者: Louri, Ahmed