Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to $\times 10$ ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.

提供了基于最近提出的Gate Workfunction工程（WFE）方法，对利用超模型逻辑门的低于10-NM逻辑构建块进行了广泛的分析。 WFE在触点中设置了WF，以及双极肖特基棒（SB）FinFET的两个独立门，以更改两个通道的阈值，作为一种独特的杠杆作用，可在单个晶体管中修改逻辑功能。因此，单个晶体管（1T）CMOS PASS-GATE，2T NAND和NON GATES以及3T或4T XOR大门，总面积（50％）和功率（最多$ \ times 10 $）的大幅降低，可以是耗散的实施的。为了利用这一潜力并说明了这些紧凑的双极晶体管的能力，新的逻辑构建块，包括6T多路复用器，8T全加速器，4T闩锁，6T D型type type flip-flop和4T和4T和Onvert（AOI）门，开发。除了使用7-nm设备进行逻辑验证外，还分析了所提出的逻辑电路的动态性能。比较模拟研究表明，独立门本SB-FINFET中的WFE可以导致绝对极简主义的CMOS逻辑块，而不会显着降低整体功率 - 播放产品（PDP）性能。