Offchip Interconnect Signaling Scheme with Near Zero Simultaneous Switching Noise

具有近零同步开关噪声的片外互连信令方案

• 批准号: 0967134
• 负责人: Madhavan Swaminathan
• 金额: $ 36万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-05-15 至 2013-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0967134&HistoricalAwards=false
• 关键词: Offchip; Interconnect; Signaling; Scheme; Near

The objective of this research is to develop a signaling scheme that produces near zero simultaneous switching noise for I/O circuits switching in a package or printed circuit board. In present packages and printed circuit boards, this is caused by the cavity resonances produced between the power and ground planes due to return path discontinuities. The approach is to replace the power planes using transmission lines that are matched at the source, thereby leading to un-interrupted current return paths. This approach can be applied to both 2D and 3D integrated systems.Intellectual Merit: Today's electronic systems use a low impedance power distribution network. Contrary to this practice, high impedance transmission lines can be used to supply power, thereby eliminating the need for hundreds of capacitors. Using the proposed interconnection topology, it is expected that copper wires in the package would be sufficient to achieve a bandwidth of 1.6TBps or better between multi-core processors and memory.Broader Impacts: The high-risk, far-reaching approach investigated in this program is beyond the current focus of the electronics industry, and thus lends itself to university-based research and development. The findings from this research and the approaches developed will be integrated into graduate and undergraduate courses. K-12 students and high school teachers are expected to participate in research, which provides engineering exposure and stimulates engineering interest.

本研究的目的是开发一种信号发送方案，为封装或印刷电路板中的 I/O 电路切换产生接近零的同步切换噪声。在目前的封装和印刷电路板中，这是由于返回路径不连续性而在电源层和接地层之间产生的空腔谐振引起的。该方法是使用在源端匹配的传输线替换电源层，从而实现不间断的电流返回路径。这种方法可应用于 2D 和 3D 集成系统。智力优点：当今的电子系统使用低阻抗配电网络。与这种做法相反，可以使用高阻抗传输线来供电，从而消除了对数百个电容器的需要。使用所提出的互连拓扑，预计封装中的铜线足以在多核处理器和内存之间实现 1.6TBps 或更好的带宽。 更广泛的影响：本研究中研究的高风险、影响深远的方法该计划超出了电子行业当前的重点，因此适合以大学为基础的研究和开发。这项研究的结果和开发的方法将纳入研究生和本科生课程。 K-12 学生和高中教师应参与研究，从而提供工程接触机会并激发工程兴趣。