Machine-Learning-Driven Synthesis Methodologies for Analog and RF Integrated Circuits in Advanced Nanometer Technologies

先进纳米技术中模拟和射频集成电路的机器学习驱动合成方法

• 批准号: RGPIN-2019-04130
• 负责人: Zhang, Lihong
• 金额: $ 2.84万
• 依托单位: Memorial University of Newfoundland
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2021
• 资助国家: 加拿大
• 起止时间: 2021-01-01 至 2022-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=737429
• 关键词: Machine; Learning; Driven; Synthesis; Methodologies

As the conventional planar CMOS technology scales down to 22nm and below, maintaining ideal transistor characteristics becomes increasingly challenging. For this reason, nonplanar field-effect transistors (FETs) have been regarded as effective substitutes for ultimate scaling. Due to physical complexity of the nonplanar FET structure in advanced nanometer technologies, transistor performance is strongly affected by associated parasitics, layout dependent effects (LDEs), and lithographic imperfection. To maintain signal integrity, these issues have to be seriously considered in the synthesis of analog/RF integrated circuits (ICs). In this research program, the fascinating advancement of artificial intelligence will be leveraged to promote electronic design automation (EDA) of analog/RF ICs. A complete set of synthesis methodologies and computer-aided design tools will be studied to strengthen the link between performance optimization and physical effects. An innovative machine-learning-driven circuit topology synthesis methodology will be developed. It can emulate expert human designers to apply the knowledge extracted from the given training data to effectively generate proper circuit topologies through inference. Moreover, a novel parasitic/LDE/lithography-aware circuit-sizing methodology will be studied; this methodology would consist of a quick approximate optimization stage followed by a simulation-based refined sizing process. Parasitics, LDEs, and lithographic effects in the advanced nonplanar nanometer technologies will be integrated into MOSFET modeling, which can be included into the topology synthesis and circuit sizing for proactive consideration of layout impact. Furthermore, to fill the vacuum of similar commercial tools in the EDA market, we will continue to explore automated analog/RF layout migration strategies to address parasitics, LDEs, and lithography-related constraints in the nonplanar nanometer technologies. Due to their high sensitivity to complicated analog effects, analog/RF ICs have been recognized as the design bottleneck for promptly pushing mixed-signal system-on-chip products to market. Systematic countermeasures in the layout-aware comprehensive synthesis of analog/RF ICs have not yet been addressed worldwide. With enormous potential for commercialization, this proposed research program addresses the increasingly challenging parasitics, LDEs, and lithographic issues in the nonplanar nanometer technologies; these issues cannot be ignored for analog/RF IC synthesis especially under the shrinking design window and pressing process variation. This program will train over half a dozen next-generation highly qualified personnel (HQP) on advanced EDA in upgraded nanometer technologies. It will benefit the analog/RF design community through significant improvements in design productivity and reliability, which can enhance Canada's competitive advantage in this field.

随着传统平面 CMOS 技术尺寸缩小至 22 纳米及以下，保持理想的晶体管特性变得越来越具有挑战性。因此，非平面场效应晶体管 (FET) 被视为最终微缩的有效替代品。由于先进纳米技术中非平面 FET 结构的物理复杂性，晶体管性能受到相关寄生效应、布局相关效应 (LDE) 和光刻缺陷的强烈影响。为了保持信号完整性，在模拟/射频集成电路 (IC) 的综合过程中必须认真考虑这些问题。在该研究计划中，人工智能的令人着迷的进步将被用来促进模拟/射频 IC 的电子设计自动化 (EDA)。将研究一整套综合方法和计算机辅助设计工具，以加强性能优化和物理效果之间的联系。将开发一种创新的机器学习驱动的电路拓扑综合方法。它可以模仿人类设计专家，应用从给定训练数据中提取的知识，通过推理有效地生成正确的电路拓扑。此外，还将研究一种新颖的寄生/LDE/光刻感知电路尺寸方法；该方法将包括快速近似优化阶段，然后是基于模拟的细化尺寸调整过程。先进非平面纳米技术中的寄生效应、LDE 和光刻效应将集成到 MOSFET 建模中，这些模型可以包含在拓扑综合和电路尺寸调整中，以便主动考虑布局影响。此外，为了填补 EDA 市场中类似商业工具的真空，我们将继续探索自动模拟/射频布局迁移策略，以解决非平面纳米技术中的寄生效应、LDE 和光刻相关限制。 由于其对复杂模拟效应的高度敏感性，模拟/射频IC已被认为是混合信号片上系统产品快速推向市场的设计瓶颈。模拟/射频 IC 的布局感知综合综合中的系统对策尚未在全球范围内得到解决。该研究计划具有巨大的商业化潜力，旨在解决非平面纳米技术中日益具有挑战性的寄生效应、LDE 和光刻问题；对于模拟/射频 IC 合成来说，这些问题不容忽视，尤其是在设计窗口不断缩小和工艺变化紧迫的情况下。该计划将培训六名以上下一代高素质人才 (HQP)，使其掌握升级纳米技术的高级 EDA。它将通过设计生产力和可靠性的显着提高使模拟/射频设计界受益，从而增强加拿大在该领域的竞争优势。