Synergistic Synthesis Methodologies and Computer-Aided Design Tools for Analog and RF Integrated Circuits in Advanced Technologies

先进技术中模拟和射频集成电路的协同综合方法和计算机辅助设计工具

• 批准号: 342185-2013
• 负责人: Zhang, Lihong
• 金额: $ 2.11万
• 依托单位: Memorial University of Newfoundland
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2018
• 资助国家: 加拿大
• 起止时间: 2018-01-01 至 2019-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=669690
• 关键词: Synergistic; Synthesis; Methodologies; Computer; Aided

Transistor performance in the 90nm and below technologies is strongly affected by extrinsic layout-dependent effects (LDEs), such as transistor well proximity and stress effects. Recent research has shown that ignoring LDEs at nanometer process nodes can cause 15%-30% variation in the transistor performance, which may readily lead to malfunction of analog/RF integrated circuits (IC). When using leading-edge commercially available analog/RF design methodologies, the associated LDE impact on circuit performance is unknown before the layout is generated. Thus, a large number of design iterations as well as manual intervention are inevitably required in advanced technologies. **In this research program, synergistic synthesis methodologies and computer-aided design tools will be studied to make a fusion between performance optimization and physical effects. An LDE- and variation-aware circuit topology synthesis methodology, which can effectively explore the search space proactively by considering associated layout impact, will be developed. A novel two-stage LDE-, variation- and parasitic-aware circuit- sizing methodology, which first deploys a symbolic-equation-based scheme for quick global optimization and then a simulation-based method for refined sizing, will be studied. We will also investigate automatic layout synthesis strategies to address LDE-, variation- and parasitic-related constraints. **Analog/RF ICs have been recognized as the design bottleneck for promptly pushing mixed-signal system-on- chip products to market due to high sensitivity to the complicated analog effects. Systematic countermeasures in the LDE-aware synthesis of analog/RF ICs have not yet been addressed worldwide. With enormous potential for commercialization, this proposed research program addresses the increasingly challenging LDE problems and their profound interactive nature that cannot be ignored for analog/RF IC synthesis in nanometer technolo- gies. This program will benefit the analog/RF design community through significant improvements in design productivity and reliability, and will enhance Canada's competitive advantage in this field.****************

90 纳米及以下技术中的晶体管性能受到外在布局相关效应 (LDE) 的强烈影响，例如晶体管阱邻近效应和应力效应。最近的研究表明，忽略纳米工艺节点的 LDE 可能会导致晶体管性能出现 15%-30% 的变化，这很容易导致模拟/射频集成电路 (IC) 发生故障。当使用领先的商用模拟/射频设计方法时，在生成布局之前，相关的 LDE 对电路性能的影响是未知的。因此，先进技术不可避免地需要大量的设计迭代和人工干预。 **在本研究计划中，将研究协同合成方法和计算机辅助设计工具，以实现性能优化和物理效果之间的融合。将开发一种 LDE 和变化感知电路拓扑综合方法，该方法可以通过考虑相关布局影响来主动有效地探索搜索空间。将研究一种新颖的两级 LDE、变化和寄生感知电路尺寸调整方法，该方法首先部署基于符号方程的方案进行快速全局优化，然后采用基于仿真的方法进行精细尺寸调整。我们还将研究自动布局综合策略，以解决 LDE、变化和寄生相关的约束。 **由于对复杂模拟效应的高度敏感性，模拟/射频 IC 已被认为是混合信号片上系统产品快速推向市场的设计瓶颈。模拟/射频 IC 的 LDE 感知综合中的系统对策尚未在全球范围内得到解决。该研究项目具有巨大的商业化潜力，旨在解决日益具有挑战性的 LDE 问题及其深刻的交互性质，这些问题对于纳米技术中的模拟/射频 IC 合成来说是不可忽视的。该计划将通过显着提高设计生产力和可靠性来使模拟/射频设计界受益，并将增强加拿大在该领域的竞争优势。****************