Synergistic Synthesis Methodologies and Computer-Aided Design Tools for Analog and RF Integrated Circuits in Advanced Technologies

先进技术中模拟和射频集成电路的协同综合方法和计算机辅助设计工具

• 批准号: 342185-2013
• 负责人: Zhang, Lihong
• 金额: $ 2.11万
• 依托单位: Memorial University of Newfoundland
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=572469
• 关键词: Synergistic; Synthesis; Methodologies; Computer; Aided; Synergistic; Synthesis; Methodologies; Computer; Aided

Transistor performance in the 90nm and below technologies is strongly affected by extrinsic layout-dependent effects (LDEs), such as transistor well proximity and stress effects. Recent research has shown that ignoring LDEs at nanometer process nodes can cause 15%-30% variation in the transistor performance, which may readily lead to malfunction of analog/RF integrated circuits (IC). When using leading-edge commercially available analog/RF design methodologies, the associated LDE impact on circuit performance is unknown before the layout is generated. Thus, a large number of design iterations as well as manual intervention are inevitably required in advanced technologies. In this research program, synergistic synthesis methodologies and computer-aided design tools will be studied to make a fusion between performance optimization and physical effects. An LDE- and variation-aware circuit topology synthesis methodology, which can effectively explore the search space proactively by considering associated layout impact, will be developed. A novel two-stage LDE-, variation- and parasitic-aware circuit- sizing methodology, which first deploys a symbolic-equation-based scheme for quick global optimization and then a simulation-based method for refined sizing, will be studied. We will also investigate automatic layout synthesis strategies to address LDE-, variation- and parasitic-related constraints. Analog/RF ICs have been recognized as the design bottleneck for promptly pushing mixed-signal system-on- chip products to market due to high sensitivity to the complicated analog effects. Systematic countermeasures in the LDE-aware synthesis of analog/RF ICs have not yet been addressed worldwide. With enormous potential for commercialization, this proposed research program addresses the increasingly challenging LDE problems and their profound interactive nature that cannot be ignored for analog/RF IC synthesis in nanometer technolo- gies. This program will benefit the analog/RF design community through significant improvements in design productivity and reliability, and will enhance Canada's competitive advantage in this field.

90nm和以下技术中的晶体管性能受到外部布局依赖性效应（LDE）的强烈影响，例如晶体管井接近和应力效应。最近的研究表明，在纳米过程节点上忽略LDE会导致晶体管性能的15％-30％变化，这可能很容易导致模拟/RF集成电路（IC）的故障。当使用前沿可用的模拟/RF设计方法时，在生成布局之前，相关的LDE对电路性能的影响尚不清楚。因此，在高级技术中不可避免地需要大量的设计迭代以及手动干预。 在该研究计划中，将研究协同合成方法和计算机辅助设计工具，以在性能优化和物理效果之间融合。将开发出一种可以通过考虑相关的布局影响来积极地主动探索搜索空间的LDE和变异感电路拓扑合成方法。将研究一种新型的两阶段LDE，变异和寄生感应电路大小的方法，该方法将首先部署基于符号方程式的方案，以快速全局优化，然后研究基于模拟的精制尺寸方法。我们还将研究以解决LDE，变异和寄生虫相关约束的自动布局综合策略。 由于对复杂的模拟效应的敏感性，模拟/RF IC被认为是迅速将混合信号系统芯片产品推向市场的设计瓶颈。在全球范围内，尚未解决模拟/RF IC的LDE征收合成中的系统对策。凭借巨大的商业化潜力，该提出的研究计划解决了越来越具有挑战性的LDE问题及其深刻的互动性质，对于纳米技术技术中的模拟/RF IC综合，这些问题不容忽视。该计划将通过显着提高设计生产率和可靠性来使模拟/RF设计社区受益，并将提高加拿大在该领域的竞争优势。