Bringing Field-Programmable Gate Arrays to the Masses: Towards a Design Eco-System

将现场可编程门阵列推向大众：迈向设计生态系统

• 批准号: RGPIN-2017-04683
• 负责人: Wilton, Steven
• 金额: $ 4.23万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2020
• 资助国家: 加拿大
• 起止时间: 2020-01-01 至 2021-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=709302
• 关键词: Bringing; Field; Programmable; Gate; Arrays

For decades, improvements in integrated circuit (IC) technology have provided dramatic increases in computing power, enabling applications such as the low-cost high-speed internet and mobile computing. New applications are on the horizon, including embedded machine-learning algorithms, extreme “big data” computation problems, and applications associated with the emerging internet of things. However, advances in many of these important applications are being held back by the lack of sufficient power-efficient and cost-effective computing hardware capabilities. Due to the increased cost and technical challenges in manufacturing smaller and faster transistors, we can no longer rely on improvements in semiconductor technology to provide the required computing horsepower. This has led to a revolution in the computing industry. Many researchers now see hardware accelerators, and in particular accelerators based on Field-Programmable Gate Arrays (FPGAs), as a disruptive technology that can provide power-efficient computing capacity necessary for many of these emerging applications. For years, FPGAs have been extremely successful as low-cost, low-risk replacements for custom integrated circuits. However, as evidenced by Intel's recent acquisition of Altera, and Microsoft's efforts to bring FPGA technology to the “cloud”, FPGAs are now poised to emerge as mainstream software accelerators. Before FPGAs can evolve into this new role, critical challenges must be addressed. Hardware accelerators will only become ubiquitous if they can be designed, optimized, and debugged by software designers and domain experts. There has been significant effort developing high-level synthesis compilers which convert software code to a hardware design. However, a compiler is not enough. Software designers expect an entire eco-system which provides the ability to characterize, evaluate, optimize and iterate on their designs quickly. The proposed Discovery Grant project will be the backbone of a research program aimed at making FPGA acceleration accessible to software designers, by making such an ecosystem a reality. Specifically, the research will focus on three aspects: (1) an iterative design flow that brings the benefits of agile methodologies to hardware design, (2) improved core compilation technologies, and (3) improved device architectures. Together, these efforts will help make ubiquitous hardware acceleration a reality, enabling many emerging applications that are simply not feasible today.

几十年来，集成电路（IC）技术的进步极大地提高了计算能力，使得低成本高速互联网和移动计算等新应用即将出现，包括嵌入式机器学习算法、极限计算等。 “大数据”计算问题以及与新兴物联网相关的应用程序然而，由于缺乏足够的节能和经济高效的计算硬件能力，这些重要应用程序的进步受到阻碍。由于制造更小、更快的晶体管的成本和技术挑战，我们不能再依靠半导体技术的改进来提供所需的计算能力，这引发了计算行业的一场革命，现在许多研究人员将硬件加速器，特别是基于现场可编程门阵列（FPGA）的加速器视为一种颠覆性技术。多年来，FPGA 作为定制集成电路的低成本、低风险替代品一直非常成功，英特尔最近收购了 FPGA。 Altera 和 Microsoft 将 FPGA 技术引入“云”的努力，FPGA 现在已准备好成为主流软件加速器。 在 FPGA 发挥这一新作用之前，必须解决关键的挑战，只有软件设计人员和领域专家能够设计、优化和调试硬件加速器，硬件加​​速器才能变得普遍。然而，仅靠编译器是不够的，软件设计人员期望整个生态系统能够快速表征、评估、优化和迭代他们的设计。该研究项目的骨干旨在通过使这样的生态系统成为现实，使软件设计人员能够使用 FPGA 加速，具体而言，该研究将重点关注三个方面：(1) 迭代设计流程，将敏捷方法的优势带入硬件设计。 ，(2) 改进的核心编译技术，以及 (3) 改进的设备架构，这些努力将共同帮助实现无处不在的硬件加速，从而使许多目前根本不可行的新兴应用成为可能。