A Smart and Efficient CAD Framework for Mapping Algorithms on Field Programmable Gate Arrays

用于现场可编程门阵列映射算法的智能高效 CAD 框架

• 批准号: RGPIN-2017-04016
• 负责人: Areibi, Shawki
• 金额: $ 2.04万
• 依托单位: University of Guelph
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2022
• 资助国家: 加拿大
• 起止时间: 2022-01-01 至 2023-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=753169
• 关键词: Smart; Efficient; CAD; Framework; Mapping

Accelerating high-performance computing (HPC) applications with Field Programmable Gate Arrays (FPGAs) can potentially deliver enormous performance compared to the fixed hardware architecture of the CPU and GPU. However, many challenges and obstacles face designers today when using FPGAs. This includes the long compile time, solution quality achieved, and the problem of fitting a design onto an FPGA architecture. Accordingly, we propose to develop a smart framework that can address the problems outlined above. First, we propose to develop an effective algorithmic solution in the form of a modular multi-level adaptive congested/timing driven analytic FPGA placement tool that is capable of producing high quality results while reducing the user experience wait-time for large scale complex applications. Second, we propose a novel machine-learning based classification system for efficiently selecting (predicting) the most appropriate flow a priori for placing/routing a new circuit, based solely on features of the circuit described at the level of a net-list in addition to the FPGA architecture. The proposed system contains a training and testing stage. The training stage involves creating a trained supervised classification model for predicting several important parameters and also the best placement/routing flows for a new circuit. Given a new circuit to place, the testing (deployment) stage uses the trained classifier model to predict the most appropriate flow to use (based on the objective(s) to be optimized) and run the placement/routing flow on the circuit; and add the circuit to the training stage's database of known circuits, enabling the framework's performance to further improve as it gains experience. Beside improving the solution quality, we also plan to reduce the compile time of the CAD flow proposed by investigating techniques for reducing runtimes through investigating efficient algorithms that measure circuit similarity and also exploitation of the low synchronization overheads in GPUs. Finally, we seek to build upon our previous work that proposed a Reconfigurable Real Time Operating System (RRTOS) for FPGAs by enhancing it with hardware accelerators that should improve scheduling and allocation of tasks. The RRTOS will aid the designer from the early design stages all the way to the actual hardware implementation.The novelty and expected significance of the proposed framework:- The proposed machine learning framework for algorithm selection and parameter tuning will significantly improve the quality of solutions produced and at the same timereduce the CPU time thus enhancing the compile time of reconfigurable systems.- The overall significance of this work will be to provide Canadian industry with scalable, smart FPGA placement and routing tools that can produce high-quality solutions, while avoiding excessively long compile times.

与CPU和GPU的固定硬件体系结构相比，具有现场可编程门阵列（FPGA）的加速高性能计算（HPC）应用程序可能会提供巨大的性能。但是，今天使用FPGA时，许多挑战和障碍都面临着设计师。这包括漫长的编译时间，实现的解决方案质量以及将设计拟合到FPGA体系结构上的问题。因此，我们建议开发一个可以解决上面概述的问题的智能框架。首先，我们建议以模块化的多级自适应拥挤/定时驱动的分析FPGA放置工具的形式开发有效的算法解决方案，该解决方案能够产生高质量的结果，同时降低用户体验大规模复杂应用的等待时间。其次，我们提出了一个新型的基于机器学习的分类系统，用于有效地选择（预测）最合适的流程，这是仅基于在网络列表级别上描述的电路的特征，用于放置/路由新电路的先验流程。到FPGA架构。提出的系统包含培训和测试阶段。训练阶段涉及创建一个训练有素的监督分类模型，以预测几个重要参数，也是新电路的最佳放置/路由流。 给定一个新电路，测试（部署）阶段使用训练有素的分类器模型来预测最合适的使用流（基于要优化的目标），并在电路上运行放置/路由流；并将电路添加到训练阶段的已知电路数据库中，从而使框架的性能随着体验而进一步提高。除了提高溶液质量外，我们还计划通过研究通过研究有效的算法来减少运行时间的技术来减少CAD流的编译时间，从而减少电路相似性以及对GPU中低同步架设的开发。 最后，我们试图建立我们以前的工作，该工作通过使用硬件加速器来改善应改进任务的计划和分配的硬件加速器来提出可重新配置的实时操作系统（RRTO）。 RRTO将从早期设计阶段一直到实际硬件实施。拟议框架的新颖性和预期意义： - 拟议的用于算法选择和参数调整的机器学习框架的新颖性和预期意义将显着提高所产生的解决方案质量在同一时间的时候，CPU时间从而增强了可重新配置系统的编译时间。-这项工作的总体意义将是为加拿大行业提供可扩展的，智能的FPGA放置和路由工具，同时避免过度产生高质量的解决方案，同时避免过度漫长的编译时间。