Bringing Field-Programmable Gate Arrays to the Masses: Towards a Design Eco-System

将现场可编程门阵列推向大众：迈向设计生态系统

• 批准号: RGPIN-2017-04683
• 负责人: Wilton, Steven
• 金额: $ 4.23万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2019
• 资助国家: 加拿大
• 起止时间: 2019-01-01 至 2020-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=690759
• 关键词: Bringing; Field; Programmable; Gate; Arrays

For decades, improvements in integrated circuit (IC) technology have provided dramatic increases in computing power, enabling applications such as the low-cost high-speed internet and mobile computing. New applications are on the horizon, including embedded machine-learning algorithms, extreme “big data” computation problems, and applications associated with the emerging internet of things. However, advances in many of these important applications are being held back by the lack of sufficient power-efficient and cost-effective computing hardware capabilities. Due to the increased cost and technical challenges in manufacturing smaller and faster transistors, we can no longer rely on improvements in semiconductor technology to provide the required computing horsepower. This has led to a revolution in the computing industry. Many researchers now see hardware accelerators, and in particular accelerators based on Field-Programmable Gate Arrays (FPGAs), as a disruptive technology that can provide power-efficient computing capacity necessary for many of these emerging applications. For years, FPGAs have been extremely successful as low-cost, low-risk replacements for custom integrated circuits. However, as evidenced by Intel's recent acquisition of Altera, and Microsoft's efforts to bring FPGA technology to the “cloud”, FPGAs are now poised to emerge as mainstream software accelerators.*** Before FPGAs can evolve into this new role, critical challenges must be addressed. Hardware accelerators will only become ubiquitous if they can be designed, optimized, and debugged by software designers and domain experts. There has been significant effort developing high-level synthesis compilers which convert software code to a hardware design. However, a compiler is not enough. Software designers expect an entire eco-system which provides the ability to characterize, evaluate, optimize and iterate on their designs quickly. The proposed Discovery Grant project will be the backbone of a research program aimed at making FPGA acceleration accessible to software designers, by making such an ecosystem a reality. Specifically, the research will focus on three aspects: (1) an iterative design flow that brings the benefits of agile methodologies to hardware design, (2) improved core compilation technologies, and (3) improved device architectures. Together, these efforts will help make ubiquitous hardware acceleration a reality, enabling many emerging applications that are simply not feasible today.

几十年来，改进的电路（IC）技术在计算能力上急剧增加，使应用程序能够使用较高的高速互联网和移动计算。 “计算问题以及与新兴互联网相关的应用程序。由于缺乏充分的功能性成本有效的计算计算计算计算硬件功能。在制造较小，更快的晶体管方面，我们不能，我们不会较长的半导体技术，基于野外编程阵列（FPGAS）所需的计算马力。然而，低成本的低风险定制集成电路。发展为新的挑战，但要解决域名。软件设计人员可以通过制造这种生态系统，从而为硬件设计带来了敏捷方法的好处，（2）改进的核心编译技术，以及（3）改进的设备架构。今天根本不可行的许多新兴景象。