Fundamental Study on Low-loss SiC Power Devices Using Multi pn Junctions

使用多pn结的低损耗SiC功率器件的基础研究

基本信息

批准号：
16360153
负责人：
KIMOTO Tsunenobu
金额：
$ 9.66万
依托单位：
KYOTO UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2004
资助国家：
日本
起止时间：
2004 至 2005
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-16360153/
关键词：
Silicon Carbide Power Device MOSFET Multi pn Junction RESURF Structure デバイスシミュレーション

项目摘要

In this research project, designing and fabrication of low-loss, high-voltage silicon carbide (SiC) power devices with multi pn junction structures have been investigated. In the multi pn junction structures, two- or three-dimensional extension of space charge regions enables the usage of highly doped semiconductors, by which on-state resistance can be significantly reduced. This is the first investigation on SiC power devices with such structures. As a typical device, lateral high-voltage MOSFETs have been investigated.Effects of doping concentration of each region on breakdown voltage and on-resistance of SiC RESURF (Reduced Surface Field) MOSFETs have been analyzed by using a two-dimensional device simulator. Effective charge at the MOS interface influences the space charge region and thereby breakdown voltage. Optimum dose designing and its guideline have been determined. Double RESURF structure with a pnp layer structure is effective to reduce on-resistance. The breakdown voltage can be increased because the electric field inside the oxide is reduced.SiC Lateral RESURF MOSFETs have been fabricated on 10 μm-thick p-type epilayers. Ion implantation was employed to form RESURF, top-p, source, and drain regions. The gate oxide was grown by direct oxidation in N_3O at 1300℃. The typical channel length, RESURF length were 2〜3μm and 20μm, respectively. An original self-aigned process has been developed to fabricate double RESURF MOSFETs. A single-zone double RESURF MOSFET fabricated in this study exhibited a breakdown voltage of 750 V and a low on-resistance of 52 mΩcm^2. The original two-zone double RESURF MOSFET showed characteristics of 1380 V - 66mΩcm^2, which is the pest performance among any lateral MOSFETs ever reported.

在这个研究项目中，研究了具有多pn结结构的低损耗、高压碳化硅（SiC）功率器件的设计和制造。在多pn结结构中，空间电荷区域的二维或三维扩展。可以使用高掺杂半导体，从而显着降低导通电阻。这是对具有这种结构的SiC功率器件的首次研究，作为一种典型器件，我们对横向高压MOSFET进行了研究。掺杂的影响。通过使用二维器件模拟器，分析了 SiC RESURF（降低表面场）MOSFET 的每个区域的浓度对击穿电压和导通电阻的影响。MOS 界面上的有效电荷会影响空间电荷区域，从而影响最佳剂量。设计及其指导方针已经确定。具有pnp层结构的双RESURF结构可以有效地降低导通电阻，因为氧化物内部的电场降低了。SiC。横向 RESURF MOSFET 已在 10 μm 厚的 p 型外延层上采用离子注入形成 RESURF、顶部 p、源极和漏极区域，栅极氧化物通过在 1300℃ 的 N_3O 中直接氧化来生长。独创的双沟道长度、RESURF长度分别为2～3μm和20μm。本研究中制造的单区双 RESURF MOSFET 显示了 750 V 的击穿电压和 52 mΩcm^2 的低导通电阻。原始两区双 RESURF MOSFET 的特性为 1380 V - 66mΩcm^2。，这是迄今为止报道过的所有横向 MOSFET 中最糟糕的性能。

项目成果

期刊论文数量（26）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

1330V,67mΩcm^2 4H-SiC(0001)RESURF MOSFET

1330V，67mΩcm^2 4H-SiC(0001)RESURF MOSFET

DOI：
发表时间：
2005
期刊：
IEEE Electron Device Lett. Vol.26
影响因子：
0
作者：
H. Matsui;H. Tabata;H.Matsui;T.Kimoto他;H.Matsui;S. T. Mahmuda;T.Kimoto他;T.Kimoto他;H. Matsui;T.Kimoto
通讯作者：
T.Kimoto

Interface properties of metal-oxide-semiconductor structureson 4H-SiC{0001} and (1120) formed by N_2O oxidation

N_2O氧化形成的4H-SiC{0001}和(1120)金属-氧化物-半导体结构的界面特性

DOI：
发表时间：
2005
期刊：
Jpn.J.Appl.Phys. 44
影响因子：
0
作者：
Junli Wang;Liwei Zhao;Nam Hoai Luu;Dong Wang;Hiroshi Nakashima;H. Matsui;H. Matsui;Kimoto他;T.Kimoto他
通讯作者：
T.Kimoto他

Characterization of in-grown stacking faults in 4H-SiC(0001) epitaxial layers and its impacts on high-voltage Schottky diodes

4H-SiC(0001)外延层内生堆垛层错的表征及其对高压肖特基二极管的影响

DOI：
发表时间：
2005
期刊：
Appl.Phys.Lett. Vol.87
影响因子：
0
作者：
H. Matsui;H. Tabata;H.Matsui;T.Kimoto他;H.Matsui;S. T. Mahmuda;T.Kimoto他;T.Kimoto他;H. Matsui;T.Kimoto;T. Ohtake;H. Matsui;T.Kimoto;K. Kotani;T.Kimoto;T. Kawahara;T.Kimoto;H. Matsui;T.Kimoto;松井裕章;T.Kimoto
通讯作者：
T.Kimoto

Experimental and theoretical investigations on short-channel effects in 4H-SiC MOSFETs