Development of Comprehensive Set of LSI CAD Benchmarks

开发一套全面的 LSI CAD 基准

• 批准号: 06558041
• 负责人: ONODERA Hidetoshi
• 金额: $ 4.61万
• 依托单位: KYOTO UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Developmental Scientific Research (B)
• 财政年份: 1994
• 资助国家: 日本
• 起止时间: 1994 至 1995
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-06558041/
• 关键词: Standard Library; Symbolic Layout; LSI CAD; Comprehenseve Benchmarks; LSI Design; Standard Cell; Gate Array; ASIC

We have developed a comprehensive set of benchmarks for quantitative evaluation of LSI CAD tools. The benchmark set describes the same circuit in several levels of abstraction so that we can set up any type of benchmarks freely. A standard set of process independent libraries has been developed for the benchmark set. KUE-CHIP2 is selected for the first candidate of the comprehensive set of benchmarks.Our achivements are summarized as follows.1.The development of standard set of librariesWe have developed a standard set of process independent libraries in a form of CMOS standard cell libraries. The library set is intended to use in comprehensive benchmarks, and also for public domain free libraries for research and educational use. The standard library is not a single set of libraries but a set of library generation tools that automatically produce process specific libraries from several process parameters. Symbolic layout method is used for layout generation. Delay and power dissipation characteristics are analzed by a new analytical method that considers short circuit currents during signal transition. The standard libraries are verified by simulation and also by a test chip.2.Development of a comprehensive set of benchmarksAs the first example of the comprehensive benchmark set, we have selected KUE-CHIP2 which is a 8-bit micro processor developed for educational use. VHDL description of KUE-CHIP2 has been developed and verified by a set of test patterns for functional verification which is supplied with its original UDL/I model.3.Evaluation of a comprehensive set of benchmarksThe KUE-CHIP2 benchmark has been evaluated by performing logic synthesis down to automatic layout with the standard libraries. It is successfully evaluated using Design Compiler of Synopsis (logic synthesis) and Alliance (automatic layout).

我们已经开发了一套全面的基准，用于定量评估LSI CAD工具。基准集在几个级别的抽象中描述了相同的电路，因此我们可以自由设置任何类型的基准测试。为基准集开发了一套标准的独立库。为综合基准集的第一个候选人选择了kue-chip2。我们的成就总结如下。1。标准库的开发我们已经以CMOS标准单元格的形式开发了一组标准的过程独立库。该图书馆旨在用于全面的基准测试中，还用于用于研究和教育用途的公共领域免费图书馆。标准库不是一组库，而是一组库生成工具，它们会自动从多个过程参数中生成特定的过程库。符号布局方法用于布局生成。延迟和功率耗散特性通过一种新的分析方法来分析，该方法在信号转变过程中考虑了短路电流。标准库通过模拟和测试芯片进行了验证。2。综合基准的开发是全面基准集的第一个示例，我们选择了Kue-Chip2，它是为教育使用开发的8位微处理器。 VHDL的KUE-CHIP2描述已通过一组功能验证的测试模式进行了开发和验证，该功能验证的原始UDL/I模型提供。3。对一组基准测试的评估kue-chip2基准测试已通过对逻辑合成以与标准的标准图书馆进行自动布局来评估KUE-CHIP2基准。使用概要的设计编译器（逻辑合成）和联盟（自动布局）成功评估了它。

项目成果

H. Onodera: "Estimation of Short-Circuit Power Dissipation and Its Influence on Propagation Delay for Static CMOS Gates" Proc. IEEE ISCAS. (発表予定). (1996)

H. Onodera：“静态 CMOS 门的短路功耗及其对传播延迟的影响”Proc。IEEE ISCAS（即将发表）。

H.Onodera: "Model-Adaptable MOSFET Parameter Extraction System" IEICE Trans.Fundamentals. Vol.E78-A. 569-572 (1995)

H.Onodera：“模型自适应 MOSFET 参数提取系统”IEICE Trans.Fundamentals。

H.Onodera: "Estimation of Short Circuit Power Dissipation for Static CMOS Gates" IEICE Trans.Fundamentals. Vol.E79-A. (1996)

H.Onodera：“静态 CMOS 门的短路功耗估算”IEICE Trans.Fundamentals。

H. Onodera: "Model-Adaptable MOSFET Parameter Extraction Method Using a Common Intermediate Model" Proc. IEEE ASIC Conf.323-326 (1994)

H. Onodera：“使用通用中间模型的模型自适应 MOSFET 参数提取方法”Proc。

H.Onodera: "Model-Adaptable MOSFET Parameter Extraction Method Using a Common Intermediate Model" Proc.IEEE ASIC Conf.323-326 (1994)

H.Onodera：“使用通用中间模型的模型自适应 MOSFET 参数提取方法”Proc.IEEE ASIC Conf.323-326 (1994)