Studies on a Hierarchical CAD System for Analog LSIs

模拟LSI分层CAD系统的研究

• 批准号: 62460127
• 负责人: TAMARU Keikichi
• 金额: $ 4.99万
• 依托单位: Kyoto University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for General Scientific Research (B)
• 财政年份: 1987
• 资助国家: 日本
• 起止时间: 1987 至 1988
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-62460127/
• 关键词: Analog LSI; CAD System; Hierarchical Design; Symbolic Layout; Layout Editor; Methodology of Block Placement; Compaction; オペアンプの自動設計; アナログ回路; LSI; レイアウト; 回路解析; 回路記述; 自動設計; デバイスシミュレータ; Analog LSI; CAD System; Hierarchical Design; Symbolic Layout; Layout Editor; Methodology of Block Placement; Compaction; オペアンプの自動設計; アナログ回路; LSI; レイアウト; 回路解析; 回路記述; 自動設計; デバイスシミュレータ

With rapid progress in integrated circuit technologies, there is a growing demand for analog LSIs and mixed analog/digital LSIs. Existing CAD systems for LSI, however, mainly put their target on handle digital circuits. Few system can treats analog circuits, which makes the design cost of full custom analog circuits prohibitively high. Therefore, it is strongly required to establish the design methodology and CAD tool for analog circuits.In this research project, we have investigated a CAD system for analog LSIs which has been constructed on the same framework as CAD systems for digital LSIs. Special interests have been put on the following points: how to introduce the concept of hierarchical design, how to manage the correspondence between circuit and layout, how to automate the optimization of various design parameters, and how to describe the design data for analog circuits. Brief descriptions of the obtained results are shown below.1. Studies on an automatic synthesis system for analog circuits: A method has been proposed that utilizes a non-linear optimization technique for the determination of design parameters in analog circuits. This method is applied to an automatic design system for operational amplifiers which generates layout of an optimally designed circuit from its performance specifications.2. Development of a hierarchical symbolic layout design system: A new layout design methodology using data description with correspondence between circuit and layout has been proposed. Based on the methodology, we have developed a symbolic layout design system which adopts newly developed hierarchical compaction method.3. Studies on design language for analog circuits: To establish a design language for mixed analog/digital LSI, we participate an activity of standardization of LSI design language for JIS. By the above research activities, we obtained fundamental techniques for analog LSI CAD systems.

随着集成电路技术的快速发展，对模拟LSI和混合模拟/数字LSI的需求不断增长。但是，现有的LSI CAD系统主要将其目标放在手柄数字电路上。很少有系统可以治疗模拟电路，这使得完整的自定义模拟电路的设计成本过高。因此，强烈需要建立用于模拟电路的设计方法和CAD工具。在这项研究项目中，我们研究了一种模拟LSIS的CAD系统，该系统已在与数字LSIS的CAD系统相同的框架上构建。特殊兴趣已在以下几点上：如何介绍层次设计的概念，如何管理电路和布局之间的对应关系，如何自动化各种设计参数的优化以及如何描述模拟电路的设计数据。所获得结果的简要描述如下所示。1。对模拟电路自动合成系统的研究：已经提出了一种方法，该方法利用非线性优化技术来确定模拟电路中的设计参数。此方法应用于用于操作放大器的自动设计系统，该系统从其性能规范中生成了最佳设计电路的布局。2。层次符号布局设计系统的开发：已提出了使用数据描述的新布局设计方法，并提出了电路和布局之间的对应关系。基于该方法，我们开发了一种符号布局设计系统，该设计系统采用了新开发的层次压实方法3。模拟电路的设计语言研究：为混合模拟/数字LSI建立设计语言，我们参与了JIS LSI设计语言的标准化活动。通过上述研究活动，我们获得了模拟LSI CAD系统的基本技术。