A research on silicon nano-devices for single-electron, quantum, CMOS integrated circuits operating at room temperature

室温下运行的单电子、量子、CMOS集成电路的硅纳米器件研究

• 批准号: 16201029
• 负责人: HIRAMOTO Toshiro
• 金额: $ 31.7万
• 依托单位: The University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (A)
• 财政年份: 2004
• 资助国家: 日本
• 起止时间: 2004 至 2007
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-16201029/
• 关键词: Nanoelectronics; MOSFET; Single-Electron Transistor; Quantum Effect Device; Coulomb Blockade; CMOS; Functional Device; Analog Pattern Matching Circuit; 量子效果デバイス; ナノテクノロジー; CMOS回路; 量子効果; 室温動作

This research aims at a new concept of integrate circuit in which new functional devices utilizing single-electron/quantum effect and conventional CMOS devices are merged operating at room temperature. At first, the fabrication process of single-electron transistors was developed. The world largest peak-to-valley current ratios of Coulomb blockade oscillations and negative differential conductance at room temperature were successfully obtained. Furthermore, the precise control of the peak position of the Coulomb blockade oscillations was achieved for the first time in single-hole transistors which have very small quantum dots. The unique characteristics originate from large quantum energy spacing in the quantum dot. Next, the integration of single-electron transistors operating at room temperature was pursued. The process conditions were finely tuned and finally, the single-electron transistors operating at room temperature were successfully integrated for the first time. Moreover, analog pattern matching circuits were fabricated by integrating single-electron transistors and their operations were demonstrated at room temperature.

这项研究旨在集成电路的新概念，在该概念中，利用单电子/量子效应和常规CMOS设备的新功能设备在室温下合并。首先，开发了单电子晶体管的制造过程。在室温下，世界最大的峰值震荡振荡和负差分电导率得到了成功。此外，在具有非常小的量子点的单孔晶体管中，首次实现了库仑阻滞振荡的峰位置的精确控制。独特的特征源自量子点中的大量子能间距。接下来，追求在室温下运行的单电子晶体管的整合。过程条件进行了细调，最后，在室温下运行的单电子晶体管首次成功集成。此外，通过整合单电子晶体管制造了模拟图案匹配电路，并在室温下进行了操作。

项目成果

Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors

• DOI: 10.1063/1.2192637
• 发表时间: 2006-04
• 期刊: Applied Physics Letters
• 影响因子: 4
• 作者: K. Miyaji;M. Saitoh;T. Hiramoto

Mobility Enhancement in Uniaxially Strained (110) Oriented Ultra-Thin Body Single- and Double-Gate MOSFETs with SOI Thickness of Less Than 4 nm

• DOI: 10.1109/iedm.2007.4419046
• 发表时间: 2007-12
• 期刊: 2007 IEEE International Electron Devices Meeting
• 作者: K. Shimizu;T. Hiramoto

High Functionality in Room-Temperature Operating Single-Electron Transistors and Silicon Nanocrystal Memories

室温操作单电子晶体管和硅纳米晶体存储器的高功能

• 发表时间: 2004
• 作者: Eiji;Nagasawa;Toshiro Hiramoto (Invited)
• 通讯作者: Toshiro Hiramoto (Invited)

FinFETType Silicon Nanocrystal Memories with Ultranarrow Channel

具有超窄通道的 FinFET 型硅纳米晶体存储器

• 发表时间: 2005
• 作者: Kosuke Yanagidaira;Masumi Saitoh;Toshiro Hiramoto
• 通讯作者: Toshiro Hiramoto

Mobility Enhancement due to Volume Inversion in (110)-oriented Ultra-thin Body Double-gate nMOSFETs with Body Thickness less than 5 nm

体厚度小于 5 nm 的 (110) 取向超薄体双栅 nMOSFET 由于体积反转而增强迁移率

• 发表时间: 2005
• 作者: Gen Tsutsui;Masumi Saitoh;Takuya Saraya;Toshiharu Nagumo;Toshiro Hiramoto
• 通讯作者: Toshiro Hiramoto