Basic research on ultra-low voltage MOS transistors aiming at sub-100mV operation

针对亚100mV运行的超低压MOS晶体管基础研究

• 批准号: 25630135
• 负责人: HIRAMOTO Toshiro
• 金额: $ 2.58万
• 依托单位: The University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Challenging Exploratory Research
• 财政年份: 2013
• 资助国家: 日本
• 起止时间: 2013-04-01 至 2014-03-31
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-25630135/
• 关键词: 電子デバイス・集積回路; 超低エネルギー; 半導体物性; MOSトランジスタ; 大規模集積回路; 超低消費電力; サブスレッショルド; 電子デバイス・機器; 低消費電力; 電子デバイス・集積回路; 超低エネルギー; 半導体物性; MOSトランジスタ; 大規模集積回路; 超低消費電力; サブスレッショルド; 電子デバイス・機器; 低消費電力

The objective of this research is to develop a semiconductor device operating at as low as 100mV. In order to obtain high on/off ratio at low voltage, a MOS transistor with a floating gate is proposed, where threshold voltage (Vth) automatically decreases in the ON state while Vth increases in the OFF state. The device was actually fabricated, and the decrease in Vth in the ON state and the increase in Vth in the OFF stage was demonstrated at as low as 100mV. It was also demonstrated that the stability of an SRAM cell was improved at 100mV.

这项研究的目的是开发以低至100mV的速度运行的半导体设备。为了在低压下获得高/关节，提出了具有浮栅极的MOS晶体管，其中阈值电压（VTH）在ON状态下自动降低，而VTH在OFF状态下增加。该设备实际上是在制造的，并且在ON状态下VTH的减小和偏离阶段的VTH的增加在低至100mV的情况下显示出来。还证明，SRAM细胞的稳定性在100mV时得到了改善。