Collaborative Research: SHF: Medium: A Comprehensive Modeling Framework for Cross-Layer Benchmarking of In-Memory Computing Fabrics: From Devices to Applications

协作研究：SHF：Medium：内存计算结构跨层基准测试的综合建模框架：从设备到应用程序

• 批准号: 2347024
• 负责人: Kai Ni
• 金额: $ 42.82万
• 依托单位: University of Notre Dame
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-11-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2347024&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Medium; Comprehensive

This project will develop a framework for rapid and accurate design-space explorations of application-level workloads assuming technology-enabled in-memory computing (IMC), which is at present being investigated for a range of application spaces (AI/machine learning, bioinformatics, graph processing, etc.). IMC is of great interest as more and more compute workloads must process ever growing amounts of data. Frequently, the energy and latency associated with data transfer from a computer’s memory to a processor can overwhelm the cost of the processing itself. As such, it is highly desirable to co-locate processing and memory. Work in the project will result a publicly available, curated framework that leverages both existing device models and design tools, and that incorporates new device models and design tools to properly evaluate the IMC design space with at-scale, application-level workloads. A modeling and evaluation infrastructure will be developed to address the above design/evaluation challenges as there is an obvious need to explore a vast design space. Investigators in this project will also work with K-8 teachers to augment existing STEM curricula with material that exposes students to fundamental concepts and skills in computer science. This is especially relevant as computer science concepts are now assessed on state-wide standardized tests. Students from under-represented groups will be recruited and mentored via REU experiences.To explore the IMC design space, device-level modeling, circuit/architectural-level modeling, device non-ideality (e.g., variation) analysis, and ways to integrate heterogeneous architectural solutions that target specific application-level workloads must all be studied. In the IMC space, (i) the number of candidate technologies is large and ever-changing, (ii) multiple candidate IMC circuits and architectures – e.g., computing at the array periphery (CAP), content addressable memories (CAMs) and crossbars – exist, (iii) IMC solutions may be more susceptible to device variations/non-idealities, and this impact must be captured at the application level, (iv) emerging technology-enabled IMC solutions may be used with existing architectural solutions and/or in a variety of heterogenous designs, and (v) there are effectively an infinite number of application-level mappings/potential algorithmic changes that one might consider. With respect to device models, there is a deliberate focus on ferroelectric devices – i.e., front-end-of-line silicon ferroelectric field effect transistors, back-end-of-line metal-oxide ferroelectric field effect transistors, and multi-gate ferroelectric field effect transistors – owing to ever-growing interest in this technology as well as the need to consider monolithic 3D processing/memory systems. For IMC circuits/architectures, this project will expand and develop modeling/evaluation tools for two different “flavors” of computing in memory – (i) CAMs (that can report memory entries that best match a given query) and (ii) CAP. For CAMs, representative efforts include projecting figures of merit for binary, ternary, multi-level, and analog CAM arrays (read/write energy and latency, etc.) designs implemented with different non-volatile memories, for different matching functions. Determining optimal CAM array sizes and other design parameters will also be considered. Evaluation of CAP designs for different NVMs will also be developed. For applications, solutions based on IMC fabrics for a subset of applications from MLPerf will be evaluated. MLPerf represents a consortium of AI leaders who have derived relevant workloads for vision, language, etc.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

该项目将开发一个框架，用于快速、准确地探索应用程序级工作负载的设计空间，假设技术支持内存计算（IMC），目前正在针对一系列应用程序空间（人工智能/机器学习、生物信息学）进行研究随着越来越多的计算工作负载必须处理不断增长的数据量，IMC 引起了人们的极大兴趣。通常，与从计算机内存到处理器的数据传输相关的能量和延迟可能会压垮整个系统。因此，非常希望将处理和内存放在一起，从而形成一个公开可用的、精心设计的框架，该框架利用现有的设备模型和设计工具，并结合了新的设备模型和技术。由于研究人员显然需要探索广阔的设计空间，因此将开发建模和评估基础设施来解决上述设计/评估挑战。该项目还将与 K-8 教师合作现有的增强 STEM 课程，让学生了解计算机科学的基本概念和技能，这一点尤其重要，因为计算机科学概念现在将通过全州标准化测试进行评估，而来自代表性不足群体的学生将通过 REU 进行招募和指导。要探索 IMC 设计空间、器件级建模、电路/架构级建模、器件非理想性（例如变化）分析以及集成针对特定应用程序级工作负载的异构架构解决方案的方法，必须全部在 IMC 领域，(i) 候选技术数量庞大且不断变化，(ii) 多种候选 IMC 电路和架构 - 例如，阵列外围计算 (CAP)、内容可寻址存储器 (CAM)。和交叉开关 – 存在，(iii) IMC 解决方案可能更容易受到设备变化/非理想的影响，并且必须在应用程序级别捕获这种影响，(iv) 新兴技术支持的 IMC 解决方案可以与现有架构一起使用解决方案和/或各种异构设计，以及（v）实际上存在无限数量的应用级映射/潜在的算法变化，人们可能会考虑到设备模型，特别关注铁电设备 -即前端硅铁电场效应晶体管、后端金属氧化物铁电场效应晶体管和多栅极铁电场效应晶体管——由于人们对该技术以及考虑单片 3D 处理/内存系统的需求，对于 IMC 电路/架构，该项目将扩展和开发两种不同的内存计算“风格”的建模/评估工具 - (i) CAM（可以）。报告与给定查询最匹配的内存条目）和 (ii) 对于 CAM，代表性工作包括预测二进制、三元、多级和模拟 CAM 阵列的品质因数（读/写）。还将考虑针对不同的匹配功能，对不同 NVM 的 CAP 设计进行评估。基于 IMC 结构的 MLPerf 应用子集的解决方案将接受评估 MLPerf 代表了一个由人工智能领导者组成的联盟，他们已经导出了视觉、语言等方面的相关工作负载。该奖项反映了 NSF 的法定使命，并已被视为。值得通过使用基金会的智力优点和更广泛的影响审查标准进行评估来支持。