Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications

合作研究：CMOS X：用于新兴计算应用的 CMOS 上大规模集成 FeFET 的设备到架构联合开发和演示

• 批准号: 2404874
• 负责人: Kai Ni
• 金额: $ 24万
• 依托单位: University of Notre Dame
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2404874&HistoricalAwards=false
• 关键词: Collaborative; Research; CMOS+X; Device; Architecture

In the new era of AI, modern computing electronics are facing tremendous challenges when a large amount of computing tasks, e.g. robotics, AR/VR, autonomous driving, require supports of gigantic computing models and enormous computing workloads. Such demands have dwarfed the capabilities of existing electronic hardware. As CMOS technology approaches 1 nm node, it is obvious that the conventional technology scaling will soon run out of steam to meet the ever-growing demand of computing power. To continue the Moore’s law, HfO2 based ferroelectric field effect transistor (FeFET) is one of the leading candidates with benefits of combined nonvolatility, high energy efficiency, and compatibility with CMOS. While many device-level developments have been performed on FeFET, one of the hindering factors is that the device’s development is often performed at small scale without high-level integration with CMOS technology, which is necessary to deliver a complete integrated-circuit (IC) solution for supporting the modern computing tasks. To overcome the limitation of existing developments, this proposal will develop cross-layer techniques from device to circuit and architecture enabling large-scale integration of the highly promising FeFET device with standard CMOS technology. This project will perform full-stack developments from device to architecture for the integration of CMOS and FeFET technology targeting emerging computing applications. Fabricated FeFET with CMOS at advanced technology nodes at a large scale will be used to demonstrate the proposed techniques. More specifically, we will perform the following developments. At device level, improved process for integration between nFeFET, pFeFET and CMOS will be developed allowing better technology fusion of the FeFET and CMOS devices; At design methodology, a joint device-circuit collaborative design flow will be developed to tailor the FeFET technology towards the need of emerging computing applications such as AI; Furthermore, novel circuit and architecture utilizing FeFET as both memory and computing devices will be developed to exploit the features of FeFET and its co-existence with CMOS technology; Finally, demonstrations on complex processors and accelerators for emerging applications, with joint CMOS and FeFET technology will be delivered to showcase the benefits of the emerging device integrated with CMOS. The integrative approach and demonstration of CMOS and FeFET fusion will manifest the system perspective of FeFET devices and establish a solid foundation for the future FeFET developments especially for the emerging computing tasks. By integrating the advanced semiconductor technology with emerging computing tasks, the proposed projects provide strong educational materials and opportunities for students to learn the multi-disciplinary developments of modern computing techniques and microelectronic devices. Both course materials and workshops on frontier semiconductor and computing techniques will be developed to provide solid training to the society while also promoting diversity and inclusion to college STEM education.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在人工智能的新时代，现代计算电子面临着巨大的挑战，大量的计算任务，例如机器人、AR/VR、自动驾驶，需要庞大的计算模型和巨大的计算工作负载的支持，这些需求使计算机的能力相形见绌。随着 CMOS 技术接近 1 nm 节点，传统技术的扩展显然很快就会失去动力，无法满足不断增长的计算能力需求，以继续摩尔定律为基础。铁电场效应晶体管 (FeFET) 是领先的候选器件之一，具有非易失性、高能效和与 CMOS 兼容等优点。虽然许多器件级开发都是在 FeFET 上进行的，但阻碍该器件发展的因素之一是。通常是小规模执行，无需与 CMOS 技术进行高级集成，而 CMOS 技术是提供支持现代计算任务的完整集成电路 (IC) 解决方案所必需的。层该项目将针对新兴计算应用进行从器件到架构的全堆栈开发，以集成 CMOS 和 FeFET 技术。大规模先进技术节点的 CMOS 将用于演示所提出的技术。更具体地说，我们将在器件级别进行以下开发，将开发用于 nFeFET、pFeFET 和 CMOS 之间集成的改进工艺，从而实现更好的技术。 FeFET 和 CMOS 器件的融合；在设计方法上，将开发一种联合器件-电路协作设计流程，以适应 AI 等新兴计算应用的需求，进一步开发利用 FeFET 作为存储器的新颖电路和架构；将开发计算设备，以利用 FeFET 的特性及其与 CMOS 技术的共存；最后，将提供针对新兴应用的复杂处理器和加速器以及 CMOS 和 FeFET 联合技术的演示，以展示其优势CMOS 与 FeFET 融合的集成方法和演示将体现 FeFET 器件的系统前景，并通过将先进的半导体技术与新兴计算任务相结合，为未来 FeFET 的发展奠定坚实的基础。新兴的计算任务，拟议的项目为学生提供了强大的教育材料和机会，让他们学习现代计算技术和微电子设备的多学科发展，将开发有关前沿半导体和计算技术的课程材料和研讨会，为学生提供扎实的培训。社会同时还促进大学 STEM 教育的多样性和包容性。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。