SHF: Small: Explainable Machine Learning for Better Design of Very Large Scale Integrated Circuits
SHF:小:可解释的机器学习,用于更好地设计超大规模集成电路
基本信息
- 批准号:2322713
- 负责人:
- 金额:$ 59.98万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2023
- 资助国家:美国
- 起止时间:2023-09-15 至 2026-08-31
- 项目状态:未结题
- 来源:
- 关键词:
项目摘要
With the advance of chip technology, Computer-Aided Design of Integrated Circuits (IC-CAD) becomes more complex, challenging, and time-consuming. Recent years have seen a rising trend of artificial intelligence (AI) applied to different stages of chip design and manufacturing. The incorporation of AI has been shown to make the chip design process more efficient and reliable by providing early feedback to predict potential failures within the design cycle. The goal of this project is to utilize the emerging field of Explainable Artificial Intelligence (XAI) to transform the utility of AI within the chip design process. This project is immediately relevant to AI-assisted chip design by providing an important explainability dimension. Explainability provides an understanding of why a design is predicted to be failing and root-causing it. It also allows the designer to identify the best strategy to avoid the failure from occurring later in the design cycle. Explanations made with XAI have the potential to transform the traditional chip design process by providing effective and early feedback about AI-predicted failures, enhancing trustworthiness to AI predictions, and overall developing a novel paradigm for designers to collaborate with the IC-CAD tools. Research findings from this project will be of immediate interest to IC-CAD and chip design companies because of their promise to reduce time-to-market of electronic products and align well with the 2022 Semiconductor CHIPS Act. The project will provide research opportunities for top undergraduate students, primarily targeting women and minorities. The investigator will present research findings of this project to domestic semiconductor and IC-CAD companies to provide opportunities for internship, employment, and collaboration which directly contribute to workforce development and enhance competitiveness of the United States in the global semiconductor market. The tasks in the project cover a wide range of cases within the chip design flow including: (1) investigating how XAI can be used to avoid design rule violations on the chip layout early-on in the design cycle; (2) investigating how XAI can better guide optimizations related to synthesis of machine learning applications in hardware; (3) investigating the benefits of XAI for chip layout obfuscation against AI-based security attacks.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
随着芯片技术的发展,集成电路(IC-CAD)的计算机辅助设计变得更加复杂,具有挑战性和耗时。近年来,人工智能(AI)的趋势不断上升,该趋势应用于芯片设计和制造的不同阶段。通过提供早期反馈来预测设计周期内潜在的故障,AI的合并已显示出可以使芯片设计过程更加高效和可靠。该项目的目的是利用可解释的人工智能(XAI)的新兴领域来改变芯片设计过程中AI的效用。该项目通过提供重要的解释性维度立即与AI辅助芯片设计相关。解释性提供了一种理解,为什么预测设计会失败和引起根源。它还允许设计师确定最佳策略,以避免在设计周期后期发生故障。用XAI做出的解释有可能通过提供有关AI预测的失败的有效和早期反馈,增强对AI预测的信任度,并总体开发一个新颖的范式,以使设计师与IC-CAD工具合作开发新颖的范式。该项目的研究结果将引起IC-CAD和芯片设计公司的立即感兴趣,因为它们有望降低电子产品的市场上市时间,并与2022年的2022 Semicicductor Chips Act保持一致。该项目将为顶级本科生提供研究机会,主要针对妇女和少数民族。研究人员将向国内半导体和IC-CAD公司提供研究结果,以提供实习,就业和协作的机会,这些机会直接有助于劳动力发展并增强美国在全球半导体市场中的竞争力。该项目中的任务涵盖了芯片设计流中的各种情况,包括:(1)研究如何使用XAI避免在设计周期提前筹码上违反设计规则的规则; (2)研究XAI如何更好地指导与硬件中机器学习应用程序合成相关的优化; (3)调查XAI对基于AI的安全攻击的芯片布局混淆的好处。该奖项反映了NSF的法定任务,并被认为是值得通过基金会的知识分子优点和更广泛的审查标准通过评估来获得支持的。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Azadeh Davoodi其他文献
Azadeh Davoodi的其他文献
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{{ truncateString('Azadeh Davoodi', 18)}}的其他基金
SHF: Small: Synthesis of Complex Deep Neural Networks on Distributed Resource-Constrained Devices
SHF:小型:分布式资源受限设备上复杂深度神经网络的综合
- 批准号:
2006394 - 财政年份:2020
- 资助金额:
$ 59.98万 - 项目类别:
Standard Grant
SaTC: STARSS: Small: Analysis of Security and Countermeasures for Split Manufacturing of Integrated Circuits
SaTC:STARSS:小型:集成电路分片制造的安全性及对策分析
- 批准号:
1812600 - 财政年份:2018
- 资助金额:
$ 59.98万 - 项目类别:
Standard Grant
SHF: Small: Bridging the Gap Between Global and Detailed Routing of Integrated Circuits
SHF:小型:弥合集成电路全局布线和详细布线之间的差距
- 批准号:
1608040 - 财政年份:2016
- 资助金额:
$ 59.98万 - 项目类别:
Standard Grant
CAREER: Automation Tools for Post-Silicon Debug of Timing Errors in Integrated Circuits
职业:用于集成电路时序错误的硅后调试的自动化工具
- 批准号:
1053496 - 财政年份:2011
- 资助金额:
$ 59.98万 - 项目类别:
Continuing Grant
SHF:Small:Parallel ILP-Based Global Routing on A Grid of Multi-Cores
SHF:Small:多核网格上基于并行 ILP 的全局路由
- 批准号:
0914981 - 财政年份:2009
- 资助金额:
$ 59.98万 - 项目类别:
Standard Grant
CPA-DA: Robust Performance Characterization in Complex VLSI Design Under Variations
CPA-DA:复杂 VLSI 设计变化下的稳健性能表征
- 批准号:
0811082 - 财政年份:2008
- 资助金额:
$ 59.98万 - 项目类别:
Continuing Grant
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