CPA-DA: Robust Performance Characterization in Complex VLSI Design Under Variations

CPA-DA：复杂 VLSI 设计变化下的稳健性能表征

• 批准号: 0811082
• 负责人: Azadeh Davoodi
• 金额: --
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-01 至 2011-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811082&HistoricalAwards=false
• 关键词: CPA; DA; Robust; Performance; Characterization

Proposal No: 811082Title: Robust Performance Characterization in Complex VLSI Design Under Variations PI name: Davoodi, Azadeh Institution: University of Wisconsin-MadisonABSTRACT:Design of Integrated Circuits is highly impacted by the imperfections of the nano-scale manufacturing process. These imperfections translate into variations in the characteristics of devices and their interconnections. These variations tend to become more random and less systematic as technology further scales down into sub-45nm domain. Only partial statistical information might be known about these variations, such as their average, variance and range. Furthermore, depending on the stage in the hierarchical design flow, correlations in the variability of the components on the chip may be partially known. Given this partial information, robust performance estimation is required to obtain more predictability during the design process. A robust prediction should include all scenarios that match with the partially available variability data. The PI proposes to investigate the novel applications of two statistical and optimization-based approaches for robust modeling of the performance of VLSI circuits. The PI suggests investigating the applicability of these approaches for large circuit sizes and large number of die-to-die and within-die variations at different stages of the design flow.Successful implementation of the proposed research allows a more predictable design flow which can make a significant contribution in the development of next generation Integrated Circuits by shortening design cycles, thereby allowing a faster time-to-market. Reducing the time-to-market can prevent losses of 5-10% magnitude per month in major manufacturing industries. In addition, the PI plans development of a graduate-level course which will likely appeal to the students outside the Computer Engineering area towards meeting their secondary and minor area requirements, at the University of Wisconsin-Madison. This research will catalyze the PI?s efforts to increase the diversity in engineering by encouraging women to study computer engineering and choose it as a career, either at industry or academia.

提案编号：811082TITLE：复杂VLSI设计中的鲁棒性能表征PI名称：Davoodi，Azadeh Institution：Wisconsin-MadisonAbstract：综合电路设计：纳米尺度制造过程的缺陷受到高度影响。这些缺陷转化为设备特征及其互连的变化。随着技术进一步扩展到亚45nm域，这些变化往往会变得更加随机和系统性。只有部分统计信息就可以了解这些变化，例如它们的平均值，差异和范围。此外，根据层次设计流的阶段，芯片上组件的变异性的相关性可能是部分已知的。鉴于此部分信息，需要进行稳健的性能估算以在设计过程中获得更多可预测性。强大的预测应包括与部分可用可变性数据匹配的所有方案。 PI建议研究两种基于统计和优化的方法的新颖应用，以实现VLSI电路性能的鲁棒建模。 PI建议调查这些方法在设计流的不同阶段的大型电路尺寸以及大量的模拟和斗争内变化的适用性。拟议的研究的实施实施允许更可预测的设计流，从而可以通过缩短综合设计环境，从而使下一代集成电路的开发能够为换乘循环，从而允许使用限制时间表，从而可以为换取时间表。缩短市场时间可以防止主要制造行业每月损失5-10％。此外，PI计划开发研究生级课程，该课程可能会吸引计算机工程领域以外的学生，以满足威斯康星大学麦迪逊分校的中学和次要区域要求。这项研究将通过鼓励妇女学习计算机工程并将其作为行业或学术界的职业选择来促进PI为增加工程多样性的努力。