CPA-DA: Robust Performance Characterization in Complex VLSI Design Under Variations

CPA-DA：复杂 VLSI 设计变化下的稳健性能表征

• 批准号: 0811082
• 负责人: Azadeh Davoodi
• 金额: --
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-01 至 2011-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811082&HistoricalAwards=false
• 关键词: CPA; DA; Robust; Performance; Characterization

Proposal No: 811082Title: Robust Performance Characterization in Complex VLSI Design Under Variations PI name: Davoodi, Azadeh Institution: University of Wisconsin-MadisonABSTRACT:Design of Integrated Circuits is highly impacted by the imperfections of the nano-scale manufacturing process. These imperfections translate into variations in the characteristics of devices and their interconnections. These variations tend to become more random and less systematic as technology further scales down into sub-45nm domain. Only partial statistical information might be known about these variations, such as their average, variance and range. Furthermore, depending on the stage in the hierarchical design flow, correlations in the variability of the components on the chip may be partially known. Given this partial information, robust performance estimation is required to obtain more predictability during the design process. A robust prediction should include all scenarios that match with the partially available variability data. The PI proposes to investigate the novel applications of two statistical and optimization-based approaches for robust modeling of the performance of VLSI circuits. The PI suggests investigating the applicability of these approaches for large circuit sizes and large number of die-to-die and within-die variations at different stages of the design flow.Successful implementation of the proposed research allows a more predictable design flow which can make a significant contribution in the development of next generation Integrated Circuits by shortening design cycles, thereby allowing a faster time-to-market. Reducing the time-to-market can prevent losses of 5-10% magnitude per month in major manufacturing industries. In addition, the PI plans development of a graduate-level course which will likely appeal to the students outside the Computer Engineering area towards meeting their secondary and minor area requirements, at the University of Wisconsin-Madison. This research will catalyze the PI?s efforts to increase the diversity in engineering by encouraging women to study computer engineering and choose it as a career, either at industry or academia.

提案编号：811082 标题：复杂 VLSI 设计变化下的鲁棒性能表征 PI 名称：Davoodi, Azadeh 机构：威斯康星大学麦迪逊分校 摘要：集成电路设计深受纳米级制造工艺缺陷的影响。这些缺陷转化为设备及其互连特性的变化。随着技术进一步缩小到 45 纳米以下领域，这些变化往往变得更加随机和不那么系统化。可能只知道有关这些变化的部分统计信息，例如它们的平均值、方差和范围。此外，根据分层设计流程中的阶段，芯片上组件的可变性的相关性可能是部分已知的。考虑到这些部分信息，需要进行稳健的性能估计，以便在设计过程中获得更多的可预测性。稳健的预测应包括与部分可用的变异性数据相匹配的所有场景。 PI 建议研究两种基于统计和优化的方法的新颖应用，以对 VLSI 电路的性能进行稳健建模。 PI 建议研究这些方法对于大电路尺寸以及设计流程不同阶段的大量芯片间和芯片内变化的适用性。所提出的研究的成功实施可以实现更可预测的设计流程，从而使通过缩短设计周期，从而加快上市时间，对下一代集成电路的开发做出了重大贡献。缩短上市时间可以防止主要制造业每月 5-10% 的损失。此外，PI 计划在威斯康星大学麦迪逊分校开发一门研究生课程，这可能会吸引计算机工程领域以外的学生，以满足他们的中学和辅修领域的要求。这项研究将鼓励 PI 鼓励女性学习计算机工程并选择其作为工业界或学术界的职业，从而促进 PI 努力增加工程领域的多样性。