PECASE: Novel Approaches for Integration of Vertical Si Nanoelectronics

PECASE：垂直硅纳米电子集成的新方法

• 批准号: 0093815
• 负责人: Veena Misra
• 金额: --
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-02-01 至 2008-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0093815&HistoricalAwards=false
• 关键词: PECASE; Novel; Approaches; Integration; Vertical

PECASE: Novel Approaches for Integration of Vertical Si NanoelectronicsVeena MisraThis proposal will investigate novel approaches in the integration of high-K dielectrics and metal gates with vertical CMOS devices. This integration offers low temperature compatibility since high-K gatestack formation in vertical devices can be performed after the source/drain regions are defined, thus avoiding any high temperature exposure. This offers tremendous opportunity for achieving ultimate CMOS performance. Within the integration scheme, several novel approaches will be evaluated. Thin layers of metals placed on grown SiO2 layers will be used to convert SiO2 to a high-K layer. Chemical vapor deposition of low metal content SiO2 layers will be evaluated for their high dielectric constant, low leakage current, and excellent mobility. Metal gates will be integrated using CVD processing and workfunction modulation will also be explored. The integration knowledge obtained will be evaluated on a novel self-assembled device in which both channel length and channel thickness are lithography independent. In the education plan, several initiatives will be pursued such as: a) organization of a workshop on integration challenges of vertical devices, b) development of a new course (classroom and web-based) in EE at NCSU entitled "Beyond Bulk CMOS", c) development of a 30-min video tape on nano-chip technology, and d) development of a "nano-chip kit" that will include a microscope, Si wafer, discrete MOSFET, an integrated circuit chip, human hair and cross-sectional scanning and transmission electron micrographs of nanoscale feaures. The goal here is to excite young students (K-12) about nanotechnology by providing them with an early exposure to this fast growing field.

PECASE：垂直Si Nanoelectronicsveena misrathis提案的整合的新方法将研究在将高K电介质和金属大门与垂直CMOS设备相结合的新方法。这种集成提供了低温兼容性，因为在定义了源/排水区域后可以执行垂直设备中的高K Gatestack形成，从而避免了任何高温暴露。这为实现最终CMOS性能提供了巨大的机会。在集成方案中，将评估几种新颖的方法。 放置在生长Sio2层上的金属薄层将用于将SIO2转换为高K层。低金属含量SiO2层的化学蒸气沉积将用于其高介电常数，低泄漏电流和出色的迁移率。金属门将使用CVD处理进行集成，还将探索工作功能调制。获得的集成知识将在一种新型的自组装装置上进行评估，其中通道长度和通道厚度均独立于光刻。 在教育计划中，将采取几项举措，例如：a）组织垂直设备集成挑战的研讨会，b）在NCSU的EE开发新课程（基于教室和网络），题为“超越散装CMOS” ，c）开发有关纳米芯片技术的30分钟录像带，以及d）开发“纳米芯片套件”，其中将包括显微镜，Si Wafer，离散MOSFET，Inctect - 纳米尺度的扫描和透射电子显微照片。这里的目的是通过为纳米技术激发年轻学生（K-12），以使他们早期接触这个快速发展的领域。